The benefits of the ordering technique to improve the static linearity performances of digital-to-analog converters are discussed. Different techniques of grouping or sequencing elements are studied for segmented, binary or unary DAC architectures. The statistic of ordered elements and their properties are reviewed and studied. Then, the optimal selection of elements for a binary or unary use is discussed. The paper also estimates the limit caused by gradient, a systematic offset, and a non detected interval in the comparator used for the sorting. Results show that the use of segmented architecture with 8~16 groups of elements sorted and optimally selected grants 2~3 bits more in the performance. The benefit can become 5 bits for 128 groups at the cost of more significant efforts for the ordering.

中文翻译：

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DAC 中单元元件的阶次统计和优化选择以增强静态线性度

讨论了排序技术改善数模转换器静态线性性能的好处。针对分段、二进制或一元 DAC 架构研究了不同的分组或排序元素技术。回顾和研究了有序元素的统计量及其性质。然后，讨论了用于二元或一元用途的元素的最佳选择。该论文还估计了用于排序的比较器中由梯度、系统偏移和未检测到的间隔引起的限制。结果表明，使用对 8~16 组元素进行排序和优化选择的分段架构可使性能提高 2~3 位。对于 128 组，好处可以变成 5 位，但代价是要付出更多的努力来进行排序。