This paper presents a wakeup timer in 40-nm CMOS for Internet-of-Things (IoT) applications based on a bang-bang Digital-intensive Frequency-Locked Loop (DFLL). A self-biased $\Sigma \Delta $ Digitally Controlled Oscillator (DCO) is locked to an RC time constant via a feedback loop consisting of a single-bit chopped comparator and a digital loop filter, thus maximizing the use of digital circuits while keeping only the RC network and the comparator as the sole analog blocks. Analysis and behavior level simulations of the DFLL have been carried out to guide the optimization of the long-term stability and frequency accuracy of the timer. High frequency accuracy and a $10\times $ enhancement of long-term stability is achieved by the adoption of chopping to reduce the effect of comparator offset and 1/f noise and by the use of $\Sigma \Delta $ modulation to improve the DCO resolution. Such highly digitized architecture fully exploits the advantages of advanced CMOS processes, thus enabling operation down to 0.7 V and a small area (0.07 mm²). The proposed timer achieves the excellent energy efficiency (0.57 pJ/cycle at 417 kHz at 0.8-V supply) over prior art while keeping excellent on-par long-term stability (Allan deviation floor < 20 ppm) and temperature stability (33 ppm°Cat 0.8-V supply).

中文翻译：

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基于 Bang-Bang 数字密集锁频环的 33-ppm/°C 240-nW 40-nm CMOS 唤醒定时器，适用于物联网应用

本文介绍了一种基于 bang-bang 数字密集锁频环 (DFLL) 的 40 纳米 CMOS 唤醒定时器，用于物联网 (IoT) 应用。一个自我偏见 $\Sigma \Delta $ 数控振荡器 (DCO) 通过由单比特斩波比较器和数字环路滤波器组成的反馈环路锁定到 RC 时间常数，从而最大限度地利用数字电路，同时仅保留 RC 网络和比较器作为唯一模拟块。对 DFLL 进行了分析和行为级模拟，以指导优化定时器的长期稳定性和频率精度。高频精度和 $10\times $ 通过采用斩波来降低比较器偏移和 1/f 噪声的影响，并通过使用 $\Sigma \Delta $ 调制以提高 DCO 分辨率。这种高度数字化的架构充分利用了先进 CMOS 工艺的优势，从而实现了低至 0.7 V 和小面积 (0.07 mm ² ) 的操作。与现有技术相比，所提出的定时器实现了出色的能效（0.57 pJ/周期，417 kHz，0.8 V 电源），同时保持出色的长期稳定性（艾伦偏差底限 < 20 ppm）和温度稳定性（33 ppm° Cat 0.8V 电源）。