A single-chip, bidirectional brain–computer interface (BBCI) enables neuromodulation through simultaneous neural recording and stimulation. This article presents a prototype BBCI application-specified integrated circuit (ASIC) consisting of a 64-channel time-multiplexed recording front-end, an area-optimized four-channel high-voltage compliant stimulator, and electronics to support the concurrent multi-channel stimulus artifact cancellation. Stimulator power generation is integrated on a chip, providing ±11-V compliance from low-voltage supplies with a resonant charge pump. High-frequency (~3 GHz) self-resonant clocking is used to reduce the pumping capacitor area while suppressing the associated switching losses. A 32-tap least mean square (LMS)-based digital adaptive filter achieves 60-dB artifact suppression, enabling simultaneous neural stimulation and recording. The entire chip occupies 4 mm² in a 65-nm low power (LP) process and is powered by 2.5-/1.2-V supplies, dissipating $205~\mu \text{W}$ in recording and $142~\mu \text{W}$ in the stimulation and cancellation back-ends. The stimulation output drivers achieve 31% dc–dc efficiency at a maximum output power of 24 mW.

中文翻译：

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标准 CMOS 中具有高压激励和自适应伪像消除的单芯片双向神经接口

单芯片双向脑机接口 (BBCI) 通过同步神经记录和刺激实现神经调节。本文介绍了一个原型 BBCI 专用集成电路 (ASIC)，它由一个 64 通道时分复用记录前端、一个面积优化的四通道高压兼容刺激器和支持并发多通道的电子设备组成。刺激伪影消除。刺激器发电集成在一个芯片上，通过带有谐振电荷泵的低电压电源提供 ±11V 一致性。高频 (~3 GHz) 自谐振时钟用于减少泵浦电容器面积，同时抑制相关的开关损耗。基于 32 抽头最小均方 (LMS) 的数字自适应滤波器实现 60-dB 伪影抑制，能够同时进行神经刺激和记录。整个芯片占据4mm²采用 65 纳米低功耗 (LP) 工艺，由 2.5-/1.2-V 电源供电，耗散 $205~\mu \text{W}$ 在录音和 $142~\mu \text{W}$ 在刺激和取消后端。刺激输出驱动器以 24 mW 的最大输出功率实现 31% 的 dc-dc 效率。