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A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage-Time Two-Step ADC With Feedforward Ring Oscillator-Based TDCs
IEEE Journal of Solid-State Circuits ( IF 5.4 ) Pub Date : 2020-07-01 , DOI: 10.1109/jssc.2020.2987699
Yifan Lyu , Filip Tavernier

A power and area efficient two-step hybrid voltage–time ADC achieves a 4-GS/s conversion speed and 39.9-dB SNDR in 28-nm CMOS. Two pipelined time-based converters (TBCs) with a thermometer capacitive DAC (CDAC) in the ADC lead to a high-speed and low-power operation. The pipelined architecture splits the full ADC resolution, thus relaxing the TBC complexity. The TBC consists of a voltage-domain comparator, a current-source-based voltage-to-time converter (VTC), and a ring oscillator (RO)-based time-to-digital converter (TDC) with feedforward and 2 $\times $ interpolation that achieves high conversion speed and good linearity simultaneously. The prototype ADC is fabricated in a standard 28-nm CMOS process with an active area of only 0.017mm2. The measured SNDR and SFDR are 39.9 and 47.8 dB with a Nyquist input at 4 GS/s. The FoMW and FoMS are 39.3 fJ/conv-step and 152.2 dB, respectively.

中文翻译:

具有基于前馈环形振荡器的 TDC 的 4GS/s 39.9dB SNDR 11.7mW 混合电压-时间两步 ADC

功率和面积高效的两步混合电压-时间 ADC 在 28-nm CMOS 中实现了 4-GS/s 转换速度和 39.9-dB SNDR。ADC 中带有温度计电容式 DAC (CDAC) 的两个流水线基于时间的转换器 (TBC) 可实现高速和低功耗操作。流水线架构拆分了完整的 ADC 分辨率,从而降低了 TBC 的复杂性。TBC 由电压域比较器、基于电流源的电压时间转换器 (VTC) 和基于环形振荡器 (RO) 的时间数字转换器 (TDC) 组成,具有前馈和 2 $\times $ 同时实现高转换速度和良好线性的插值。原型 ADC 采用标准 28-nm CMOS 工艺制造,有效面积仅为 0.017mm 2。测得的 SNDR 和 SFDR 分别为 39.9 和 47.8 dB,奈奎斯特输入为 4 GS/s。FoM W和 FoM S分别为 39.3 fJ /conv-step 和 152.2 dB。
更新日期:2020-07-01
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