Hysteresis-free and low-voltage operation are essential for low-power-consumption electronics. Herein, MoS₂ transistors configured with bilayer-stacked polymethyl methacrylate (PMMA)/poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) gate dielectric are demonstrated, which leverages the advantages of the hysteresis-free characteristic of PMMA and high- ${k}$ property of P(VDF-TrFE). The trap density and the threshold voltage of the devices can be reduced to $7.0\times 10^{11}$ cm $^{-2}\cdot eV^{-1}$ and −2.2 V, respectively. Moreover, the devices maintain stable performance under bias stress conditions. The devices present negligibly changed transfer and output characteristics over 101 cycling tests, indicating excellent stability. The bilayered dielectric engineering strategy provides a promising avenue to achieve hysteresis-free low-power operation in 2D materials based transistors with high stability.

中文翻译：

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具有低 k/高 k 双层栅极电介质的稳定无滞后 MoS2 晶体管

无滞后和低电压操作对于低功耗电子产品至关重要。在此，展示了由双层堆叠的聚甲基丙烯酸甲酯 (PMMA)/聚偏二氟乙烯-三氟乙烯 (P(VDF-TrFE)) 栅极电介质配置的MoS ₂晶体管，它利用了 PMMA 的无滞后特性和高—— ${k}$ P(VDF-TrFE) 的特性。器件的陷阱密度和阈值电压可以降低到 $7.0\乘以 10^{11}$ 厘米 $^{-2}\cdot eV^{-1}$ 和-2.2 V，分别。此外，器件在偏置应力条件下保持稳定的性能。这些器件在 101 次循环测试中表现出的传输和输出特性变化可以忽略不计，表明具有出色的稳定性。双层介电工程策略为在具有高稳定性的基于 2D 材料的晶体管中实现无滞后低功耗操作提供了有希望的途径。