Developing Field-programmable Gate Array (FPGA) architectures is challenging due to the competing requirements of various application domains and changing manufacturing process technology. This is compounded by the difficulty of fairly evaluating FPGA architectural choices, which requires sophisticated high-quality Computer Aided Design (CAD) tools to target each potential architecture. This article describes version 8.0 of the open source Verilog to Routing (VTR) project, which provides such a design flow. VTR 8 expands the scope of FPGA architectures that can be modelled, allowing VTR to target and model many details of both commercial and proposed FPGA architectures. The VTR design flow also serves as a baseline for evaluating new CAD algorithms. It is therefore important, for both CAD algorithm comparisons and the validity of architectural conclusions, that VTR produce high-quality circuit implementations. VTR 8 significantly improves optimization quality (reductions of 15% minimum routable channel width, 41% wirelength, and 12% critical path delay), run-time (5.3× faster) and memory footprint (3.3× lower). Finally, we demonstrate VTR is run-time and memory footprint efficient, while producing circuit implementations of reasonable quality compared to highly-tuned architecture-specific industrial tools—showing that architecture generality, good implementation quality, and run-time efficiency are not mutually exclusive goals.

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由于各种应用领域的竞争需求和不断变化的制造工艺技术，开发现场可编程门阵列 (FPGA) 架构具有挑战性。公平评估 FPGA 架构选择的难度加剧了这一点，这需要复杂的高质量计算机辅助设计 (CAD) 工具来针对每个潜在的架构。本文介绍了开源 Verilog to Routing (VTR) 项目的 8.0 版本，它提供了这样的设计流程。VTR 8 扩展了可建模的 FPGA 架构的范围，允许 VTR 以商业和提议的 FPGA 架构的许多细节为目标和建模。VTR 设计流程还可以作为评估新 CAD 算法的基准。因此，重要的是，对于 CAD 算法比较和架构结论的有效性，VTR 产生了高质量的电路实现。VTR 8 显着提高了优化质量（减少了 15% 的最小可路由通道宽度、41% 的线长和 12% 的关键路径延迟）、运行时间（快了 5.3 倍）和内存占用（降低了 3.3 倍）。最后，我们证明了 VTR 在运行时和内存占用方面是高效的，同时与高度调整的架构特定的工业工具相比，产生了质量合理的电路实现——表明架构通用性、良好的实现质量和运行时效率并不是相互排斥的目标。和 12% 的关键路径延迟）、运行时间（快 5.3 倍）和内存占用（低 3.3 倍）。最后，我们证明了 VTR 在运行时和内存占用方面是高效的，同时与高度调整的架构特定的工业工具相比，产生了质量合理的电路实现——表明架构通用性、良好的实现质量和运行时效率并不是相互排斥的目标。和 12% 的关键路径延迟）、运行时间（快 5.3 倍）和内存占用（低 3.3 倍）。最后，我们证明了 VTR 在运行时和内存占用方面是高效的，同时与高度调整的架构特定的工业工具相比，产生了质量合理的电路实现——表明架构通用性、良好的实现质量和运行时效率并不是相互排斥的目标。