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A Retargetable MATLAB-to-C Compiler Exploiting Custom Instructions and Data Parallelism
ACM Transactions on Embedded Computing Systems ( IF 2 ) Pub Date : 2020-07-07 , DOI: 10.1145/3391898
Ioannis Latifis 1 , Karthick Parashar 2 , Grigoris Dimitroulakos 1 , Hans Cappelle 3 , Christakis Lezos 1 , Konstantinos Masselos 1 , Francky Catthoor 3
Affiliation  

This article presents a MATLAB-to-C compiler that exploits custom instructions present in state-of-the-art processor architectures and supports semi-automatic vectorization. A parameterized processor model is used to describe the target instruction set architecture to achieve user-friendly retargetability. Custom instructions are represented via specialized intrinsic functions in the generated code, which can then be used as input to any C/C++ compiler supporting the target processor. In addition, the compiler supports the generation of data parallel/vectorized code through the introduction of data packing/unpacking statements. The compiler has been used for code generation targeting ARM and x86 architectures for several benchmarks. The vectorized code generated by the compiler achieves an average speedup of 4.1× and 2.7× for packed fixed and floating point data, respectively, compared to scalarized code for ARM architecture and an average speedup of 3.1× and 1.5× for packed fixed and floating point data, respectively, for x86 architecture. Implementing data parallel instructions directly in the assembly code would have required a lot of design effort, and it would not been sustainable across evolving platform variants. Thus, the compiler can be employed to efficiently speed up critical sections of the target application. The compiler is therefore potentially employable to raise the design abstraction and reduce development time for both embedded and general-purpose applications.

中文翻译:

利用自定义指令和数据并行性的可重定向 MATLAB-to-C 编译器

本文介绍了一个 MATLAB-to-C 编译器,该编译器利用了最先进的处理器架构中存在的自定义指令,并支持半自动向量化。参数化处理器模型用于描述目标指令集架构,以实现用户友好的可重定向性。自定义指令通过生成代码中的专用内部函数表示,然后可以用作支持目标处理器的任何 C/C++ 编译器的输入。此外,编译器通过引入数据打包/解包语句,支持生成数据并行/向量化代码。该编译器已用于针对 ARM 和 x86 架构的代码生成,用于多个基准测试。编译器生成的矢量化代码实现了 4.1 倍和 2 倍的平均加速。与 ARM 架构的标量化代码相比,打包定点和浮点数据分别为 7 倍,打包定点和浮点数据的平均加速分别为 x86 架构的 3.1 倍和 1.5 倍。直接在汇编代码中实现数据并行指令需要大量的设计工作,并且在不断发展的平台变体中是不可持续的。因此,可以使用编译器来有效地加速目标应用程序的关键部分。因此,编译器可用于提高设计抽象度并减少嵌入式和通用应用程序的开发时间。对于 x86 架构。直接在汇编代码中实现数据并行指令需要大量的设计工作,并且在不断发展的平台变体中是不可持续的。因此,可以使用编译器来有效地加速目标应用程序的关键部分。因此,编译器可用于提高设计抽象度并减少嵌入式和通用应用程序的开发时间。对于 x86 架构。直接在汇编代码中实现数据并行指令需要大量的设计工作,并且在不断发展的平台变体中是不可持续的。因此,可以使用编译器来有效地加速目标应用程序的关键部分。因此,编译器可用于提高设计抽象度并减少嵌入式和通用应用程序的开发时间。
更新日期:2020-07-07
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