Dynamic Random Access Memory (DRAM) standards have evolved for higher bandwidth, larger capacity, and lower power consumption, so their specifications have become complicated to satisfy the design goals. These complex implementations have significantly increased the test time overhead for design verification; thus, a tremendous amount of command sequences are used. However, since the sequences generated by real machines or memory simulators are the results of scheduling for high performance, they result in low test coverage with repetitive patterns. Eventually, various workloads should be applied to increase the coverage, but this approach incurs significant test time overhead. A few preliminary studies have been proposed to generate predefined or random sequences to cover various test cases or increase test coverage. However, they have limitations in representing various memory behaviors of real workloads. In this article, we define a performance metric for estimating the test coverage when using command sequences. Then, our experiment shows that the coverage of a real machine and a simulator is low and similar. Also, the coverage patterns are almost the same in all tested benchmarks. To alleviate the problem, we propose a test-oriented command scheduling algorithm that increases the test coverage while preserving the memory behaviors of workloads and reducing the test time overhead by extracting representative sequences based on the similarity between command sequences. For the sequence extraction and the coverage estimation, our test sequences are embedded into vectors using bag-of-Ngrams. Compared to the simulator, our algorithm achieves 2.94x higher coverage while reducing the test overhead to 7.57%.

中文翻译：

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从实际工作负载生成代表性测试序列以最小化 DRAM 验证开销

动态随机存取存储器 (DRAM) 标准已经发展为更高带宽、更大容量和更低功耗，因此它们的规格变得复杂以满足设计目标。这些复杂的实现大大增加了设计验证的测试时间开销；因此，使用了大量的命令序列。然而，由于真实机器或内存模拟器生成的序列是高性能调度的结果，它们导致重复模式的测试覆盖率低。最终，应该应用各种工作负载来增加覆盖率，但这种方法会产生大量的测试时间开销。已经提出了一些初步研究来生成预定义或随机序列以覆盖各种测试用例或增加测试覆盖率。然而，它们在表示实际工作负载的各种内存行为方面存在局限性。在本文中，我们定义了一个性能指标，用于在使用命令序列时估计测试覆盖率。然后，我们的实验表明，真机和模拟器的覆盖率较低且相似。此外，覆盖模式在所有测试基准中几乎相同。为了缓解这个问题，我们提出了一种面向测试的命令调度算法，该算法通过基于命令序列之间的相似性提取代表序列来增加测试覆盖率，同时保留工作负载的内存行为并减少测试时间开销。对于序列提取和覆盖率估计，我们的测试序列使用 bag-of-Ngrams 嵌入到向量中。与模拟器相比，我们的算法达到了2。