Untrusted foundries pose threats of integrated circuit (IC) piracy and counterfeiting, and this has motivated research into logic locking. Strong logic locking approaches potentially prevent piracy and counterfeiting by preventing unauthorized replication and use of ICs. Unfortunately, recent work has shown that most state-of-the-art logic locking techniques are vulnerable to attacks that utilize Boolean Satisfiability (SAT) solvers. In this article, we extend our prior work on using silicon nanowire (SiNW) field-effect transistors (FETs) to produce obfuscated ICs that are resistant to reverse engineering attacks, such as the sensitization attack, SAT and approximate SAT attacks, as well as tracked signal attacks. Our method is based on exchanging some logic gates in the original design with a set of polymorphic gates (PLGs), designed using SiNW FETs, and augmenting the circuit with a small block, whose output is untraceable, namely, URSAT. The URSAT may not offer very strong resilience against the combined AppSAT-removal attack. Strong URSAT is achieved using only CMOS-logic gates, namely, S-URSAT. The proposed technique, S-URSAT + PLG-based traditional encryption, designed using SiNW FETs, increases the security level of the design to robustly thwart all existing attacks, including combined AppSAT-removal attack, with small penalties. Then, we evaluate the effectiveness of our proposed methods and subject it to a thorough security analysis. We also evaluate the performance penalty of the technique and find that it results in very small overheads in comparison to other works. The average area, power, and delay overheads of implementing 64 baseline key-bits of S-URSAT for small benchmarks are 5.03%, 2.60%, and −2.26%, respectively, while for large benchmarks they are 2.37%, 1.18%, and −1.93%.

中文翻译：

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针对 IC 逆向工程攻击的低开销的强逻辑混淆

不受信任的代工厂构成集成电路 (IC) 盗版和假冒的威胁，这激发了对逻辑锁定的研究。强大的逻辑锁定方法通过防止未经授权的复制和使用 IC 来潜在地防止盗版和伪造。不幸的是，最近的工作表明，大多数最先进的逻辑锁定技术都容易受到利用布尔可满足性 (SAT) 求解器的攻击。在本文中，我们扩展了我们之前的工作，即使用硅纳米线 (SiNW) 场效应晶体管 (FET) 来生产能够抵抗逆向工程攻击的混淆 IC，例如敏化攻击、SAT 和近似 SAT 攻击，以及跟踪信号攻击。我们的方法基于用一组多态门（PLG）交换原始设计中的一些逻辑门，使用 SiNW FET 设计，并用一个输出无法追踪的小块（即 URSAT）扩充电路。URSAT 可能无法针对组合的 AppSAT 删除攻击提供非常强大的弹性。强 URSAT 仅使用 CMOS 逻辑门，即 S-URSAT 来实现。所提出的技术，基于 S-URSAT + PLG 的传统加密，使用 SiNW FET 设计，提高了设计的安全级别，以稳健地挫败所有现有攻击，包括组合 AppSAT 移除攻击，并且惩罚很小。然后，我们评估我们提出的方法的有效性，并对其进行彻底的安全分析。我们还评估了该技术的性能损失，发现与其他工作相比，它导致的开销非常小。平均面积、功率、