3D Network-on-Chip (3D NoC) enables design of high-performance and energy-efficient manycore computing platforms. Two of the commonly used vertical interconnection technologies are: through silicon via (TSV) and near-field inductive coupling (NFIC). Both TSV- and NFIC-based links introduce additional area overhead. One of the possible ways to reduce the area overhead is to design partially connected 3D NoC with minimal effect on overall performance. The achievable performance of the partially connected 3D NoCs depends on the area, energy, and bandwidth of the vertical links. Moreover, the electromigration-induced failure of TSV is more severe than the misalignment-induced error in NFIC. By considering all these pertinent factors, we demonstrate that it is indeed possible to design a partially connected NFIC-based 3D NoC that performs as good as a fully connected TSV-based counterpart when the data rate is below a certain limit. For higher data rates, the partially connected TSV-based 3D NoC is a viable solution. However, NFIC-based 3D NoC is always more robust than the TSV-based counterpart.

中文翻译：

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为部分连接的 3D NoC 提供案例

3D 片上网络 (3D NoC) 支持设计高性能和节能的众核计算平台。两种常用的垂直互连技术是：硅通孔 (TSV) 和近场感应耦合 (NFIC)。基于 TSV 和 NFIC 的链路都引入了额外的区域开销。减少面积开销的一种可能方法是设计部分连接的 3D NoC，而对整体性能的影响最小。部分连接的 3D NoC 可实现的性能取决于垂直链路的面积、能量和带宽。此外，TSV 的电迁移引起的故障比 NFIC 中的错位引起的误差更严重。通过考虑所有这些相关因素，我们证明，当数据速率低于某个限制时，确实可以设计一个部分连接的基于 NFIC 的 3D NoC，它的性能与基于 TSV 的完全连接的对应物一样好。对于更高的数据速率，部分连接的基于 TSV 的 3D NoC 是一种可行的解决方案。然而，基于 NFIC 的 3D NoC 总是比基于 TSV 的对应物更强大。