With extreme miniaturization of traditional CMOS devices in deep sub-micron design levels, the delay of a circuit, as well as power dissipation and area are dominated by interconnections between logic blocks. Interconnect today is causing major problems such as delay, power dissipation, and so on. In an attempt to search for alternative materials, Graphene nanoribbons have been found to be potential for both transistors and interconnects due to its outstanding electrical and thermal properties. Graphene nanoribbons provide better options as materials used for global routing trees in VLSI circuits. However, certain special characteristics of Graphene nanoribbon prohibit direct application of existing VLSI routing tree construction methods. In this article, we address this issue and propose heuristic methods for construction of Graphene nanoribbon--based minimum hybrid cost and minimum-delay Steiner trees. We compute the delays for the trees using Elmore delay approximation. Experimental results demonstrate the effectiveness of our proposed methods, which are quite encouraging.

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基于石墨烯纳米带的电路和互连的全局布线方法

随着传统 CMOS 器件在深亚微米设计级别的极端小型化，电路的延迟以及功耗和面积都由逻辑块之间的互连主导。今天的互连正在引起诸如延迟、功耗等重大问题。在尝试寻找替代材料的过程中，石墨烯纳米带因其出色的电学和热学特性而被发现具有用于晶体管和互连的潜力。石墨烯纳米带作为用于 VLSI 电路中全局路由树的材料提供了更好的选择。然而，石墨烯纳米带的某些特殊特性禁止直接应用现有的 VLSI 路由树构造方法。在本文中，我们解决了这个问题，并提出了构建基于石墨烯纳米带的最小混合成本和最小延迟施泰纳树的启发式方法。我们使用 Elmore 延迟近似计算树的延迟。实验结果证明了我们提出的方法的有效性，这是非常令人鼓舞的。