Since the early 70s, simulation infrastructures have been a keystone in computer architecture research, providing a fast and reliable way to prototype and evaluate ideas for future computing systems. There are different types of simulators, from most detailed (cycle-accurate) to time-based/functional and analytical modeling. Increasing accuracy translates into several orders of magnitude in terms of simulation speed. Yet, a question remains open: are the results derived from the simulation infrastructure representative of a real machine?

Validation of these infrastructures is complex and costly, usually performed upon release. However, most simulators do not provide the appropriate means to verify or validate new architectural models. In this paper, we introduce a semi-automatic validation framework based on real-hardware performance counter information. The framework provides two levels of abstraction: (a) a high level definition of the processor behavior (Top-Down model) and (b) detailed per-structure and per-pipeline-stage usage breakdown to pinpoint simulator issues. We used this framework to validate the latest available gem5-x86 simulation environment, and found several sources of error that alter the expected behavior of the simulated processor, which we were later to document and correct.

自70年代初以来，仿真基础结构一直是计算机体系结构研究的基石，它提供了一种快速可靠的方法来原型化和评估未来计算系统的构想。从最详细的（周期精确的）到基于时间的/功能的和分析的建模，模拟器的类型各不相同。在仿真速度方面，提高的精度转化为几个数量级。但是，问题仍然悬而未决：从仿真基础结构中得出的结果是否代表真实机器？

这些基础结构的验证是复杂且昂贵的，通常在发布时执行。但是，大多数模拟器都没有提供适当的方法来验证或验证新的体系结构模型。在本文中，我们介绍了一个基于真实硬件性能计数器信息的半自动验证框架。该框架提供了两个抽象层次：（a）处理器行为的高层定义（自上而下的模型），以及（b）详细的按结构和按流水线阶段划分的使用情况，以查明模拟器问题。我们使用此框架验证了最新的gem5-x86仿真环境，并发现了多种错误源，这些错误源改变了仿真处理器的预期行为，稍后我们将对其进行记录和更正。