Designing a Static Random-Access Memory (SRAM) cell configuration that copes with conventional complementary metal-oxide-semiconductor (CMOS) constraints on the cell area is desired to satisfy high packing density in integrated digital circuits. This paper analyzes and compares performance parameters of 6T SRAM bit-cells based on the side-contacted field-effect diode (S-FED) and conventional CMOS at 180 nm technology node. Steady-state responses demonstrate that in the worst-case, by applying weak logic 0/1 to the bit-lines, strong logic data is stored in the S-FED-based cell with superior write margin and lower power consumption by about one order of magnitude in comparison with the CMOS-based one. Comparing static noise margin reveals that S-FED-based cells enjoy prominent stability, especially in the read and hold operations with ~3X and 29% improvements, respectively, to the CMOS-based versions. In addition, enhancement of read-stability is attained utilizing S-FED-based cell, as well as decrement of subthreshold current and static power dissipation, compared with the CMOS-based one. Sensitivity analyses extracted from Monte Carlo simulations and butterfly curves indicate that S-FED-based cell successfully tolerates process and supply voltage variations in all operation modes, superior to the CMOS-based counterpart.

需要设计一种静态随机存取存储器（SRAM）单元配置以应对单元区域上的常规互补金属氧化物半导体（CMOS）约束，以满足集成电路数字电路中的高封装密度。本文分析并比较了基于侧接触场效应二极管（S-FED）和常规CMOS在180 nm技术节点上的6T SRAM位单元的性能参数。稳态响应表明，在最坏的情况下，通过将弱逻辑0/1应用于位线，将强逻辑数据存储在基于S-FED的单元中，具有出色的写余量和较低的功耗约一阶与基于CMOS的相比，幅度更大。比较静态噪声裕度，可以发现基于S-FED的电池具有出色的稳定性，特别是在读取和保持操作中，与基于CMOS的版本相比分别提高了约3倍和29％。此外，与基于CMOS的单元相比，利用基于S-FED的单元可以提高读取稳定性，并且可以降低亚阈值电流和静态功耗。从蒙特卡洛模拟和蝶形曲线提取的灵敏度分析表明，基于S-FED的电池在所有操作模式下都能成功地承受工艺和电源电压变化，优于基于CMOS的电池。