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A capacitor-splitting DAC switching scheme with high power-efficiency and low common-mode voltage variation
Analog Integrated Circuits and Signal Processing ( IF 1.4 ) Pub Date : 2020-06-24 , DOI: 10.1007/s10470-020-01677-y
Hao Wang , Zhixin Chen , Wenming Xie , Tianwei Chen , Haiyan Ou

In this letter, a capacitor-splitting switching algorithm for successive approximation register (SAR) analog-to-digital converters is proposed. To achieve low power, the hybrid switching scheme is involved. The monotonic switching technique is used during the last bit cycle; for other bit cycles except the first one, the switching is based on MSB and the former determined bit. Besides, the common-mode voltage remains constant during the entire bit cycles except the last one. In addition, the proposed capacitor-splitting switching process is easily performed, relaxing the design complexity of the SAR control logic. As a result, the proposed switching scheme is a better trade-off among energy-efficiency, common-mode voltage variation, and logic complexity.



中文翻译:

具有高功率效率和低共模电压变化的电容分裂DAC开关方案

在这封信中,提出了一种用于逐次逼近寄存器(SAR)模数转换器的电容器拆分开关算法。为了实现低功耗,需要使用混合开关方案。在最后一个比特周期内使用单调切换技术。对于除第一个比特周期外的其他比特周期,切换基于MSB和前一个确定的比特。此外,共模电压在除最后一个比特周期外的整个比特周期内保持恒定。此外,所提出的电容分路切换过程很容易执行,从而缓解了SAR控制逻辑的设计复杂性。结果,所提出的开关方案是在能量效率,共模电压变化和逻辑复杂度之间更好的权衡。

更新日期:2020-06-25
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