The incorporation of gaussian/multiple peak gaussian doping in planar 4H-SiC junctionless field effect transistor (JLFET) allows the conceptualization and realization of higher gate controllablity. With the aim of formulating and investigating the underlying device current gating mechanism of gaussian/multiple peak gaussian doping 4H-SiC JLFET with enhanced device performance, we have adopted the exhaustive calibrated 2D TCAD study approach. Our study suggests that by deploying either gaussian or multiple peak gaussian doping improves the I_ON/I_OFF ratio magnificently as compared to the uniformly doped planar 4H-SiC JLFET. Moreover, multiple peak gaussian doping even without the use of P⁺ pockets improves the switching behaviour as the sub-threshold slope (SS) value reduces. Interestingly, it is observed that just by incorporating the gaussian doping approach the mandate of incorporating P⁺ pockets to get better volume depletion can be relaxed. Thus the additional fabrication steps to realize the P⁺ pockets in junctionless structure can be avoided. This results in the lowering of device thermal budget and random dopant fluctuations (RDFs) immune structure. Further, as the reported device demonstrates volume/bulk conduction, it is also expected to be immune towards the interface trapped charges, hence this device realization no more needs additional fabrication steps such as counter doping and annealing to neutralize the semiconductor-oxide traps. Further, device sensitivity analysis in terms of channel length, P⁺ pockets length, fixed trapped charges at the 4H-SiC-SiO₂ interface and temperature variation has also been carried out here.

在平面4H-SiC无结场效应晶体管（JLFET）中引入高斯/多峰值高斯掺杂可以实现更高的栅极可控制性。为了制定和研究具有增强的器件性能的高斯/多峰高斯掺杂4H-SiC JLFET的潜在器件电流门控机制，我们采用了详尽的校准2D TCAD研究方法。我们的研究表明，与均匀掺杂的平面4H-SiC JLFET相比，通过部署高斯或多个峰值高斯掺杂，可以显着提高I _{O N} / I _{O F F}比率。而且，即使不使用P ⁺，也可以进行多个峰值高斯掺杂随着亚阈值斜率（SS）值的减小，口袋改善了开关性能。有趣的是，观察到仅通过结合高斯掺杂方法，就可以放松结合P ⁺口袋以获得更好的体积耗尽的任务。因此，实现P ⁺的附加制造步骤可以避免采用无结结构的口袋。这导致器件热预算和随机掺杂物波动（RDF）免疫结构的降低。此外，由于所报道的器件表现出体积/本体传导，因此还期望其不受界面捕获的电荷的影响，因此该器件的实现不再需要额外的制造步骤，例如反掺杂和退火以中和半导体氧化物阱。此外，这里还进行了关于沟道长度，P ⁺口袋长度，在4H-SiC-Si O ₂界面处固定的俘获电荷和温度变化方面的器件灵敏度分析。