Runtime variability sources, such as bias temperature instability (BTI) and supply voltage fluctuation affect both timing and functionality of the flip-flops inside a VLSI circuit. In this paper, we propose a method to improve the timing and reliability of the VLSI circuits by optimizing the flip-flops for resiliency against aging and supply voltage fluctuation. In the proposed selective reliability optimization method, we first extend the standard cell libraries by adding optimized versions of the flip-flops designed for better resiliency against severe BTI impact and/or supply voltage fluctuation. Then, we optimize the VLSI circuit by replacing the aging-critical and voltage-drop-critical flip-flops (VC) of the circuit with the reliability-optimized versions to improve the timing and the reliability of the entire circuit in a cost-effective way. The simulation results show that incorporating the optimized flip-flops in a processor can prolong the lifetime of the processor by 36.9% compared to the original design, which translates into better reliability. This is achieved with negligible leakage overhead (less than 0.1% on the processor) and no area overhead which facilitates the integration of the proposed method in the standard VLSI design flow.

中文翻译：

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可靠数字电路设计的选择性触发器优化

运行时可变性源，例如偏置温度不稳定性 (BTI) 和电源电压波动，会影响 VLSI 电路内触发器的时序和功能。在本文中，我们提出了一种通过优化触发器以提高抗老化和电源电压波动的弹性来提高 VLSI 电路的时序和可靠性的方法。在提议的选择性可靠性优化方法中，我们首先通过添加优化版本的触发器来扩展标准单元库，这些触发器旨在更好地抵御严重的 BTI 影响和/或电源电压波动。然后，我们通过用可靠性优化版本替换电路的老化关键和压降关键触发器 (VC) 来优化 VLSI 电路，以具有成本效益的方式提高整个电路的时序和可靠性办法。仿真结果表明，与原始设计相比，在处理器中加入优化的触发器可以将处理器的寿命延长 36.9%，从而转化为更好的可靠性。这是通过可忽略的泄漏开销（处理器上小于 0.1%）和无面积开销实现的，这有助于将所提出的方法集成到标准 VLSI 设计流程中。