Low power system-on-chips (SoCs) are now at the heart of Internet-of-Things (IoT) devices, which are well-known for their bursty workloads and limited energy storage—usually in the form of tiny batteries. To ensure battery lifetime, dynamic voltage frequency scaling (DVFS) has become an essential technique in such SoC chips. With continuously decreasing supply level, noise margins in these devices are already being squeezed. During DVFS transition, large current that accompanies the clock speed transition runs into or out of clock networks in a few clock cycles, induces large ${\text {L}di}{/}{\mathrm {d}t}$ noise, thereby stressing the power delivery system (PDS). Due to the limited area and cost target, adding additional decoupling capacitance to mitigate such noise is usually challenging. A common approach is to gradually introduce/remove the additional clock cycles to increase/decrease the clock frequency in steps, also known as, clock skipping. However, such a technique may increase DVFS transition time, and still cannot guarantee minimal noise. In this paper, we propose a new noise-aware DVFS sequence optimization technique by formulating a mixed 0/1 programming to resolve the problems of clock skipping sequence optimization. Moreover, the method is also extended to schedule extensive wake-up activities on different clock domains for the same purpose. The experiments show that the optimized sequence is able to significantly mitigate noise within the desired transition time, thereby saving both power and energy.

中文翻译：

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用于在电池供电的 IoT 设备上实现高效转换的噪声感知 DVFS

低功耗片上系统 (SoC) 现在是物联网 (IoT) 设备的核心，这些设备以其突发性工作负载和有限的能量存储（通常以微型电池的形式）而闻名。为确保电池寿命，动态电压频率缩放 (DVFS) 已成为此类 SoC 芯片中的一项基本技术。随着电源水平的不断降低，这些设备的噪声容限已经受到挤压。在 DVFS 转换期间，伴随时钟速度转换的大电流在几个时钟周期内流入或流出时钟网络，引起大的 ${\text {L}di}{/}{\mathrm {d}t}$ 噪声，从而对电力传输系统 (PDS) 施加压力。由于面积和成本目标有限，添加额外的去耦电容以减轻此类噪声通常具有挑战性。一种常见的方法是逐步引入/删除额外的时钟周期，以逐步增加/减少时钟频率，也称为时钟跳跃。但是，这种技术可能会增加 DVFS 转换时间，并且仍然不能保证最小的噪声。在本文中，我们提出了一种新的噪声感知 DVFS 序列优化技术，通过制定混合 0/1 编程来解决时钟跳跃序列优化的问题。此外，该方法还扩展到为同一目的在不同时钟域上安排大量唤醒活动。实验表明，优化的序列能够在所需的过渡时间内显着降低噪声，从而节省功率和能量。这种技术可能会增加 DVFS 转换时间，但仍然不能保证最小的噪声。在本文中，我们提出了一种新的噪声感知 DVFS 序列优化技术，通过制定混合 0/1 编程来解决时钟跳跃序列优化的问题。此外，该方法还扩展到为相同目的在不同时钟域上安排大量唤醒活动。实验表明，优化的序列能够在所需的过渡时间内显着降低噪声，从而节省功率和能量。这种技术可能会增加 DVFS 转换时间，但仍然不能保证最小的噪声。在本文中，我们提出了一种新的噪声感知 DVFS 序列优化技术，通过制定混合 0/1 编程来解决时钟跳跃序列优化的问题。此外，该方法还扩展到为相同目的在不同时钟域上安排大量唤醒活动。实验表明，优化的序列能够在所需的过渡时间内显着降低噪声，从而节省功率和能量。该方法还扩展到为同一目的在不同时钟域上安排大量唤醒活动。实验表明，优化的序列能够在所需的过渡时间内显着降低噪声，从而节省功率和能量。该方法还扩展到为相同目的在不同时钟域上安排大量唤醒活动。实验表明，优化的序列能够在所需的过渡时间内显着降低噪声，从而节省功率和能量。