One of the main problems in chip design is the huge number of interconnections between digital blocks. Using Multi-valued logic can lead to the reduction of interconnections. So, the chip area and power dissipation in connections could be reduced. To fulfil the multi-valued logic aim, however, the number of transistors should be reduced considerably. In this paper, first, a novel quaternary multiplexer is designed. Then, a novel method for implementing the quaternary logic with single supply voltage is proposed. In this method, first, two binary functions are defined. One of them is activated when the quaternary function is ‘1′ or ‘2’. Another one is activated when the quaternary function is ‘2′ or ‘3’. These binary functions are implemented using the proposed multiplexer. Then, an encoder will create the quaternary function from these binary functions. The number of transistors for the quaternary full-adder designs is reduced from 195 in the previous works to 68 in the proposed method. Also, as the logics ‘1′ and ‘2′ are only produced in the last stage encoder, power consumption and PDP are considerably improved. The simulation results using HSPICE and 32 ​nm Stanford library confirm the correct operation and the considerable PDP improvement from 39.45% to 99.53%, as compared to the previous works.

芯片设计中的主要问题之一是数字模块之间的大量互连。使用多值逻辑可以减少互连。因此，可以减少连接中的芯片面积和功耗。但是，为了实现多值逻辑目标，应大大减少晶体管的数量。本文首先设计了一种新型的四进制多路复用器。然后，提出了一种采用单电源电压实现四进制逻辑的新方法。在这种方法中，首先，定义了两个二进制函数。当四元函数为“ 1”或“ 2”时，将激活其中之一。当四元函数为“ 2”或“ 3”时，将激活另一个。这些二进制功能是使用建议的多路复用器实现的。然后，编码器将从这些二进制函数创建四进制函数。四元全加器设计的晶体管数量从以前的方法中的195到提出的方法中的68。另外，由于仅在最后一级的编码器中产生逻辑“ 1”和“ 2”，因此功耗和PDP得以显着改善。与以前的工作相比，使用HSPICE和32 nm Stanford库进行的仿真结果证实了正确的操作并将PDP从39.45％提高到了99.53％。