A four-stage eight-way CMOS power amplifier (PA) for 94 GHz radar sensor is reported. The PA constitutes a common-source (CS) input stage, a CS first gain stage, a two-way CS second gain stage, followed by an eight-way CS output stage using miniature triple Y-shaped divider and combiner. Broadband π-match input, inter-stage, and output networks are adopted for broadband impedance or power matching. Inductive shunt-shunt feedback technique is used at the input and the first gain stages to boost gain. This leads to a boosted saturated output power (P_sat) and power-added efficiency (PAE). At every division’s input (i.e. the drain of the parallel CS output stage), the triple Y-shaped current combiner transforms the serial RL load into the optimum load impedance (homologous to the optimum P_sat and PAE) of the output stage transistors. At supply voltage (V_DD) of 1.2 V, the PA attains P_sat of 12.1 dBm, gain of 17.5 dB, and PAE of 14.8% at 94 GHz, the best values ever demonstrated for a W-band CMOS PA in 90 nm CMOS. Moreover, at high V_DD of 2.4 V, the PA achieves high P_sat of 18.2 dBm, gain of 19.6 dB, and PAE of 15% at 94 GHz. The eminent results of the CMOS PA reveal that it is hopeful for 94 GHz radar sensor.

报告了用于94 GHz雷达传感器的四级八路CMOS功率放大器（PA）。该PA构成一个公共源（CS）输入级，一个CS第一增益级，一个两路CS第二增益级，然后是一个使用微型三重Y形分频器和组合器的八路CS输出级。宽带π匹配输入，级间和输出网络用于宽带阻抗或功率匹配。在输入和第一个增益级使用电感式分流反馈技术来提高增益。这导致饱和输出功率（P _sat）和功率附加效率（PAE）的提高。在每个分区的输入（即并行CS输出级的漏极）处，三重Y形电流组合器将串行RL负载转换为最佳负载阻抗（与最佳P _sat相同和PAE）。在1.2 V的电源电压（V _DD）下，PA在94 GHz时达到P _sat为12.1 dBm，增益为17.5 dB，PAE为14.8％，这是90 nm CMOS中W波段CMOS PA的最佳值。此外，在2.4 V的高V _DD时，在94 GHz时，PA的P _sat为18.2 dBm，增益为19.6 dB，PAE为15％。CMOS PA的杰出结果表明，它对94 GHz雷达传感器很有希望。