A machine learning (ML) design framework is proposed for dynamically adjusting clock frequency based on propagation delay of individual instructions. A Random Forest model is trained to classify propagation delays in real-time, utilizing current operation type, current operands, and computation history as ML features. The trained model is implemented in Verilog as an additional pipeline stage within a baseline processor. The modified system is simulated at the gate-level in 45 nm CMOS technology, exhibiting a speed-up of 68% and energy reduction of 37% with coarse-grained ML classification. A speed-up of 95% is demonstrated with finer granularities at additional energy costs.

中文翻译：

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流水线处理器中动态频率缩放的统一学习平台

提出了一种机器学习 (ML) 设计框架，用于根据单个指令的传播延迟动态调整时钟频率。训练随机森林模型以实时对传播延迟进行分类，利用当前操作类型、当前操作数和计算历史作为 ML 特征。经过训练的模型在 Verilog 中实现，作为基线处理器中的附加流水线阶段。修改后的系统在 45 nm CMOS 技术的门级进行了模拟，在粗粒度 ML 分类下表现出 68% 的加速和 37% 的能量降低。在额外的能源成本下，使用更细的粒度证明了 95% 的加速。