In this work, a new circuit of delay cell is proposed to design a wide tuning range differential ring oscillator (DRO). Statistical techniques of Taguchi design of experiments and analysis of variance (ANOVA) are used to optimize the performance parameters of the proposed circuit. Three levels and 3 factors of width (w1, w3 and w4) for various MOSFETs of delay cell, are considered as major performance controlling factors. Taguchi method identifies the significant level of a factor which affects the specific performance parameter. ANOVA analysis is used to find the critical factor for a specified response. This method is also used to find the optimum values of width w1, w3 and w4 for the overall optimum performance of the proposed circuit. Pre and post layout simulations are carried out in GPDK45 nm CMOS technology to justify the statistical results with the simulated ones. Proposed circuit offers wide tuning range of 88.04% (from 1.67 to 13.96 GHz), phase noise of − 91.38 dBc/Hz (at 10 MHz offset), power consumption of 6.93 mW (at Fosc = 11.34 GHz) and total chip area of \(610\,\upmu \hbox {m}^2\). The proposed DRO find its suitability in high speed communication devices, medical equipment’s and navigation systems.

在这项工作中，提出了一种新的延迟单元电路来设计宽调谐范围的差分环形振荡器（DRO）。Taguchi设计的实验统计技术和方差分析（ANOVA）用于优化拟议电路的性能参数。延迟单元的各种MOSFET的三个电平和三个宽度因子（w1，w3和w4）被视为主要的性能控制因素。Taguchi方法确定影响特定性能参数的因素的显着水平。方差分析用于查找指定响应的关键因素。该方法还用于为建议的电路的整体最佳性能找到宽度w1，w3和w4的最佳值。使用GPDK45 nm CMOS技术进行布局前和布局后仿真，以用仿真的结果证明统计结果的合理性。拟议的电路可提供88.04％（从1.67至13.96 GHz）的宽调谐范围，− 91.38 dBc / Hz的相位噪声（在10 MHz偏移时），6.93 mW的功耗（在Fosc = 11.34 GHz时）和总芯片面积\（610 \，\ upmu \ hbox {m} ^ 2 \）。提议的DRO在高速通信设备，医疗设备和导航系统中很合适。