Nowadays, the size of the hearing aid devices are reduced to make them invisible and function rapidly. As a result of these factors, an EMI is generated inside the chips. The general working principle of the hearing aid SoC is disrupted by this internal EMI. Thus, an open loop fractional dividers based all-digital clock generator is introduced in the proposed hearing aid SoC. The jitter is reduced by the use of a high resolution digital-to-time converter with its range and duty cycle calibration in background. Also, the nonlinearity of the analog front-end circuit in the proposed hearing aid SoC is reduced by introducing a switching block based dynamic element matching process. Furthermore, an improved noise reduction algorithm is proposed based on pitch based voice activity detector and multiband complex spectral subtraction to improve the performance of the proposed hearing Aid SoC. The proposed hearing aid SoC is designed in an 180 nm CMOS technology. The simulation results show that, integrated jitter of the proposed structure is reduced to 0.9 ps_rms and it achieves a signal to noise ratio of 89.24 dB. The total power consumption of this hearing aid is only 996 μW for 1.2 V supply that shows the superiority of the proposed work than existing works.

如今，助听器设备的尺寸减小了，使它们不可见并且可以快速运行。由于这些因素，芯片内部会产生EMI。内部EMI干扰了助听器SoC的一般工作原理。因此，在建议的助听器SoC中引入了基于开环分数除法器的全数字时钟发生器。通过使用高分辨率数字-时间转换器及其背景范围和占空比校准，可以减少抖动。此外，通过引入基于开关模块的动态元素匹配过程，可以减少所提出的助听器SoC中模拟前端电路的非线性。此外，提出了一种基于基音的语音活动检测器和多频带复谱减法的改进的降噪算法，以提高所提出的助听器SoC的性能。拟议的助听器SoC采用180 nm CMOS技术设计。仿真结果表明，所提出结构的综合抖动降低至0.9 ps_均方根值，信噪比为89.24 dB。对于1.2 V电源，此助听器的总功耗仅为996μW，这表明拟议的工作比现有工作优越。