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Channel-protecting fabrication of top-gate MoS 2 transistor arrays
Semiconductor Science and Technology ( IF 1.9 ) Pub Date : 2020-06-08 , DOI: 10.1088/1361-6641/ab864d
Zhenghao Gu , Hao Liu , Yang Wang , Hao Zhu , Lin Chen , Qingqing Sun , David Wei Zhang

The surface passivation on MoS 2 and other transition metal dichalcogenides (TMDs) has been widely studied and utilized to prevent contamination and oxygen/water vapor penetration. Such approaches are mostly applied on the back-gate transistors after the formation of source/drain electrodes, while the compatibility in constructing top-gate devices has not yet been experimentally explored. Here, based on the large-area MoS 2 thin film prepared with the atomic layer deposition technique, we developed an experimental routine to fabricate top-gate MoS 2 thin-film transistor arrays with the TMD channel protected by high-k dielectric during the entire device fabrication process. The channel protection is enabled by the high-quality Al 2 O 3 dielectric with proper pretreatment. The transistors in the array have shown enhanced electrical performance compared to the non-protected devices. Such a robust and well-controlled fabrication techn...

中文翻译:

顶栅MoS 2晶体管阵列的沟道保护制造

已经广泛研究了MoS 2和其他过渡金属二氢二硫化碳(TMD)上的表面钝化,并用于防止污染和氧气/水蒸气渗透。在形成源极/漏极之后,这种方法主要应用于背栅晶体管,而在构造顶栅器件方面的兼容性尚未得到实验性的探索。在这里,基于通过原子层沉积技术制备的大面积MoS 2薄膜,我们开发了一种实验程序来制造顶栅MoS 2薄膜晶体管阵列,该阵列的TMD沟道在整个过程中均受高k介电层保护设备制造过程。通过高质量的Al 2 O 3电介质并经过适当的预处理,可以实现通道保护。与不受保护的器件相比,阵列中的晶体管显示出增强的电气性能。如此强大且控制良好的制造技术...
更新日期:2020-06-08
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