In this work, we investigate the dynamic buffer response of AlInN/GaN high electron mobility transistors (HEMTs) grown on silicon substrates. Significant improvements in vertical breakdown voltage, reduced buffer conduction and charge trapping effect are observed on the samples with a superlattice layer (SL) in the buffer. The dynamic response of the buffer layer largely depends on the composition, thickness and position of the SL in the stress-mitigating buffer. The vertical breakdown voltage increases consistently with decreasing edge-type dislocations when the density of screw-type dislocations is low. Negative back-gating measurements show the lowest buffer current hysteresis in the sample with the lowest edge-type dislocation density, indicating least charge trapping in the sample. Four terminal positive back-gating measurements in the on-state, further confirm the observed trend. Based on the experimental observations, we propose that the total density of threading dislocations, (acts as vertical leakage path) and the acceptor like edge-type dislocations should be accounted along with the electron injection from the silicon substrate to the buffer. Therefore, resulting in higher vertical breakdown voltage by alleviating serious dynamic buffer response in GaN-based HEMTs.

中文翻译：

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超晶格结构对 AlInN/GaN-on-Si HEMT 动态缓冲响应的影响

在这项工作中，我们研究了在硅衬底上生长的 AlInN/GaN 高电子迁移率晶体管 (HEMT) 的动态缓冲响应。在缓冲器中具有超晶格层 (SL) 的样品上观察到垂直击穿电压、缓冲器传导降低和电荷俘获效应的显着改善。缓冲层的动态响应在很大程度上取决于应力减轻缓冲层中 SL 的组成、厚度和位置。当螺旋型位错密度较低时，垂直击穿电压随着边缘型位错的减少而持续增加。负背栅测量显示具有最低边缘型位错密度的样品中最低的缓冲电流滞后，表明样品中的电荷俘获最少。导通状态下的四端正背栅测量进一步证实了观察到的趋势。基于实验观察，我们建议将穿透位错的总密度（作为垂直泄漏路径）和像边缘型位错的受体与从硅衬底到缓冲器的电子注入一起考虑在内。因此，通过减轻 GaN 基 HEMT 中严重的动态缓冲响应，导致更高的垂直击穿电压。