In this article, a novel full-chip EM simulation tool, called EMSpice simulator is proposed. The new method starts from first principles and simultaneously considers two major interplaying physics effects in EM failure process: the hydrostatic stress and electronic current/voltage in a power grid network. The new tool starts by reading the power grid layout information from Synopsys IC Compiler. It then removes immortal interconnect wires by considering both nucleation phase immortality and incubation phase immortality for multi-segment interconnects. Thereafter, a finite difference time domain (FDTD) solver is employed for stress analysis for every mortal interconnect tree for both nucleation and post-voiding phases. At the whole power grid circuit level, the EM analysis is coupled with IR drop analysis of a whole power grid network at each time step so that we can consider the interaction among stress, void growth, resistance change and IR drop in a single simulation framework. Accuracy of EMSpice is validated by comparing with a published EM simulator, XSim, for nucleation phase, and finite element method based COMSOL for post-voiding phase. The comparison results show that EMSpice agrees well with both methods with. Experimental results on two practical processor chip designs show that the proposed coupled EM-IR drop analysis method can further reduce the overly conservative EM-aware power grid design as the number of the failed trees found by EMSpice simulator is up to 76.7% less than the Black’s method and 66.7% less than a recently proposed full-chip EM analysis method respectively. Furthermore EMSpice simulator is the least conservative one for lifetime estimation of individual tree wires among the three methods.

中文翻译：

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EMSpice：使用耦合电子和应力仿真进行基于物理的电迁移检查

在本文中，提出了一种新的全芯片 EM 仿真工具，称为 EMSpice 仿真器。新方法从第一性原理出发，同时考虑了 EM 故障过程中两个主要相互作用的物理效应：电网网络中的静水应力和电子电流/电压。新工具首先从 Synopsys IC Compiler 读取电网布局信息。然后通过考虑多段互连的成核阶段不朽和孵化阶段不朽来去除不朽的互连线。此后，采用有限差分时域 (FDTD) 求解器对成核和后空化阶段的每个必死互连树进行应力分析。在整个电网电路层面，EM 分析与每个时间步长的整个电网网络的 IR 压降分析相结合，以便我们可以在单个模拟框架中考虑应力、空隙增长、电阻变化和 IR 压降之间的相互作用。EMSpice 的准确性通过与已发布的 EM 模拟器 XSim 的成核阶段和基于 COMSOL 的后空化阶段的有限元方法进行比较来验证。比较结果表明，EMSpice 与两种方法都吻合得很好。在两个实际处理器芯片设计上的实验结果表明，所提出的耦合 EM-IR 压降分析方法可以进一步减少过于保守的 EM-aware 电网设计，因为 EMSpice 模拟器发现的故障树数量比Black 的方法和比最近提出的全芯片 EM 分析方法分别少 66.7%。