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Efficient Majority-Logic Reed-Solomon Decoders for Single Symbol Correction
IEEE Transactions on Device and Materials Reliability ( IF 2 ) Pub Date : 2020-06-01 , DOI: 10.1109/tdmr.2020.2980754
Francisco Garcia-Herrero , Alfonso Sanchez-Macian , Mateo San-Isidro , Luis Alberto Aranda , Juan Antonio Maestro

A new low-complexity method to decode single symbol correction Reed-Solomon codes is proposed in this paper. This decoding algorithm takes advantage of the equivalent parity-check matrix representation to apply majority logic techniques that avoid the needs of computing Galois Field inversions, divisions and logarithms, unlike previous efficient solutions. The derived architectures allow to increase the order of the Galois Field, keeping similar area and delay results for the same message length. Hence, it is possible to configure the burst error capacity without compromising the decoder performance. Finally, due to the three-step procedure of the decoder: syndrome, magnitude estimation and majority logic, the decoding latency is reduced to two clock cycles without compromising the critical path improving latency between two and five times. The proposed decoder can obtain an area reduction of at least 44% for codes with high Galois Field order, i.e., GF(28). The high level of customization in terms of data word length and the high frequency and low area make these decoders suitable for a wide range of storage systems.

中文翻译:

用于单符号校正的高效多数逻辑 Reed-Solomon 解码器

本文提出了一种新的低复杂度解码单符号校正Reed-Solomon码的方法。这种解码算法利用等效的奇偶校验矩阵表示来应用多数逻辑技术,避免计算伽罗瓦域反演、除法和对数的需要,这与以前的高效解决方案不同。派生的架构允许增加伽罗华域的阶数,对于相同的消息长度保持相似的面积和延迟结果。因此,可以在不影响解码器性能的情况下配置突发错误容量。最后,由于解码器的三步程序:校正子、幅度估计和多数逻辑,解码延迟减少到两个时钟周期,而不会影响关键路径,将延迟提高 2 到 5 倍。对于具有高伽罗瓦域阶数的代码,即 GF(28),所提出的解码器可以获得至少 44% 的面积减少。在数据字长以及高频和低面积方面的高度定制使这些解码器适用于广泛的存储系统。
更新日期:2020-06-01
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