As the standard complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) generates a leakage current due to ionizing radiation reacting with silicon in a radiological environment, radiation hardening of CMOS devices is being actively investigated. If a radiation-tolerant IC (RTIC) is designed, it is very important to examine the design possibility of an application specific IC (ASIC) that uses a radiation-tolerant MOS field-effect transistor (MOSFET). This study developed a new RTIC design using an I-gate structure that is more effective in terms of time, cost, and reliability than the existing RTMOSFET. Because an RTIC with an I-gate structure can be fabricated via the usual full-custom IC design process, it can be produced after its reliability is ensured based on post-layout simulation results, which are obtained by layout parasitic extraction (LPE). To realize the possibility of such fabrication, radiation-tolerant digital and analog ICs were designed and fabricated in the standard 0.18- $\mu \text{m}$ CMOS process, and an irradiation test was conducted up to a total dose of approximately 2 Mrad. Accordingly, the radiation damage in the standard IC and the radiation tolerance of the RTIC were identified. Consequently, we have proposed and verified an efficient radiation-tolerant ASIC design solution.

中文翻译：

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具有总电离剂量效应容差的高可靠性CMOS IC设计

由于标准互补金属氧化物半导体 (CMOS) 集成电路 (IC) 由于电离辐射在放射环境中与硅反应而产生泄漏电流，因此正在积极研究 CMOS 器件的辐射硬化。如果设计了耐辐射 IC (RTIC)，那么检查使用耐辐射 MOS 场效应晶体管 (MOSFET) 的专用 IC (ASIC) 的设计可能性非常重要。本研究开发了一种使用 I 栅极结构的新 RTIC 设计，在时间、成本和可靠性方面比现有的 RTMOSFET 更有效。由于具有I-gate结构的RTIC可以通过通常的全定制IC设计工艺制造，因此可以根据布局后的模拟结果确保其可靠性后生产，这些是通过布局寄生提取（LPE）获得的。为了实现这种制造的可能性，在标准 0.18-$\mu\text{m}$ CMOS 工艺中设计和制造了耐辐射数字和模拟 IC，并进行了总剂量约为 2先生。因此，确定了标准 IC 中的辐射损坏和 RTIC 的辐射耐受性。因此，我们提出并验证了一种高效的耐辐射 ASIC 设计解决方案。确定了标准 IC 中的辐射损坏和 RTIC 的辐射耐受性。因此，我们提出并验证了一种高效的耐辐射 ASIC 设计解决方案。确定了标准 IC 中的辐射损坏和 RTIC 的辐射耐受性。因此，我们提出并验证了一种高效的耐辐射 ASIC 设计解决方案。