This paper presents the design of a low-latency, highly linear current-steering DAC for use in continuous-time ADCs. A detailed analysis of equivalent unary-weighted current-steering DAC topologies in terms of mismatch, noise, and output-impedance related distortion is carried out. From this analysis, we propose a tri-level DAC design that achieves 12-bit static linearity and is suitable for implementation in a continuous-time ADC architecture. To reduce output-impedance related distortion, the design combines DAC slice impedance matching with a proposed compensation technique. By incorporating the tri-level DAC in a continuous-time ADC architecture, the technique demonstrates ~ 8dB improvement in DAC dynamic performance at high frequencies over the Nyquist-band at 100MS/s. The DAC has been verified by simulation results in TSMC 1.2V 65nm CMOS technology.

中文翻译：

---

具有适用于CT-ADC的12位线性度和改进的阻抗匹配的三级电流控制DAC的分析和设计

本文介绍了一种用于连续时间ADC的低延迟，高度线性的电流控制DAC的设计。对失配，噪声和与输出阻抗有关的失真方面的等效一元加权电流控制DAC拓扑进行了详细分析。通过该分析，我们提出了一种三级DAC设计，该设计可实现12位静态线性度，并且适合在连续时间ADC架构中实施。为了减少与输出阻抗有关的失真，该设计将DAC slice阻抗匹配与一种建议的补偿技术结合在一起。通过将三级DAC集成到连续时间ADC架构中，该技术证明了在100MS / s的奈奎斯特频带上的高频下，DAC动态性能提高了约8dB。台积电1中的仿真结果已验证了DAC。