In this letter, we propose an ultralow-power transformer-based V-band receiver front-end using a 65-nm CMOS technology. Forward-body-bias and transformer-based positive-feedback topologies are utilized to enable its operation at a low drain bias of 0.3 V, while still ensuring its gain performance. A resistive ring mixer, with its advantage of zero-dc-power consumption, serves as the frequency down-converter of the system. The proposed receiver front-end demonstrates an 8.5-dB conversion gain and possesses the power-saving ability to use only 0.7 mW of dc-power consumption.

中文翻译：

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65nm CMOS 中基于 0.7mW V 波段变压器的正反馈接收器前端

在这封信中，我们提出了一种使用 65 纳米 CMOS 技术的基于超低功耗变压器的 V 波段接收器前端。前体偏置和基于变压器的正反馈拓扑被用来使其在 0.3 V 的低漏偏置下运行，同时仍确保其增益性能。电阻环混频器具有零直流功耗的优势，可用作系统的下变频器。建议的接收器前端展示了 8.5-dB 的转换增益，并具有仅使用 0.7 mW 直流功耗的节能能力。