The modern semiconductor industry is evolving quite rapidly. Portable and mobile devices are becoming smaller every day and there is also a growing demand for longer battery power. With these demands it is important for researchers to focus on the leakage power in stand-by mode. The SRAM was designed to accurately communicate with CPU, DSP, processor and low-power applications, such as battery-life handheld devices. For some days now, the design engineer focuses mainly on the production of large-capacity memories, high bandwidth and low energy consuming memories. Memory is an integral part of most of these systems and is also diminished as the scale of the system reduces. Low power and processing architecture at high speed is therefore a major concern. The durability of random static access memory cells (SRAM) is another critical factor. This Paper Describes the SRAM architecture designed for the reduction of power consumption or power leakages using sleep transistor and MTCMOS (Multi-Threshold Complementary Metal Oxide Semiconductor) techniques. This helps in the reduction of the CMOS transistor leakages. This paper incorporates multiple threshold strategies to give the proposed high speed, increased reliability and low leakage current of the updated 8T SRAM cell in stand-by memory cell mode. Based on the parameters like power dissipation at a different temperature, read voltage, write voltage, read delay, write delay, compared to the previously designed SRAM architecture of 6T, 7T, 8T and 13T we get low power consumption in our designed 8T SRAM architecture. The simulations are conducted with the UMC 55 nm technology Cadence Virtuoso method.

现代半导体产业正在迅速发展。便携式和移动设备每天都在变小，并且对更长电池电量的需求也在不断增长。面对这些需求，研究人员必须重点关注待机模式下的泄漏功率。SRAM旨在与CPU，DSP，处理器和低功耗应用（例如具有电池寿命的手持设备）进行精确通信。如今，设计工程师几天来一直主要致力于大容量存储器，高带宽和低能耗存储器的生产。内存是大多数这些系统不可或缺的一部分，并且随着系统规模的减小而减少。因此，低功耗和高速处理架构是一个主要问题。随机静态存取存储单元（SRAM）的耐用性是另一个关键因素。本文介绍了使用睡眠晶体管和MTCMOS（多阈值互补金属氧化物半导体）技术为降低功耗或漏电而设计的SRAM架构。这有助于减少CMOS晶体管泄漏。本文结合了多种阈值策略，以在备用存储单元模式下为更新的8T SRAM单元提供拟议的高速，提高的可靠性和低泄漏电流。基于不同温度下的功耗，读取电压，写入电压，读取延迟，写入延迟等参数，与之前设计的6T，7T，8T和13T SRAM架构相比，我们设计的8T SRAM架构功耗较低。使用UMC 55 nm技术Cadence Virtuoso方法进行了仿真。