Field-programmable gate arrays (FPGAs) have recently evolved as a valuable component of the heterogeneous computing. The register transfer level (RTL) design flows demand the designers to be experienced in hardware, resulting in a possible failure of time-to-market. High-level synthesis (HLS) permits designers to work at a higher level of abstraction through synthesizing high-level language programs to RTL descriptions. This provides a promising approach to solve these problems. However, the performance of HLS tools still has limitations. For example, designers remain exposed to various aspects of hardware design, development cycles are still time consuming, and the quality of results (QoR) of HLS tools is far behind that of RTL flows. In this paper, we survey the literature published since 2014 focusing on the performance optimization of HLS tools. Compared with previous work, we extend the scope of the performance of HLS tools, and present a set of three-level evaluation criteria, covering from ease of use of the HLS tools to promotion on specific metrics of QoR. We also propose performance evaluation equations for describing the relation between the performance optimization and the QoR. We find that it needs more efforts on the ease of use for efficient HLS tools. We suggest that it is better to draw an analogy between the HLS development process and the embedded system design process, and to provide more elastic HLS methodology which integrates FPGAs virtual machines.

中文翻译：

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高级综合工具性能优化综述

现场可编程门阵列 (FPGA) 最近发展成为异构计算的重要组成部分。寄存器传输级 (RTL) 设计流程要求设计人员具备硬件方面的经验，这可能会导致上市时间失败。高级综合 (HLS) 允许设计人员通过将高级语言程序综合为 RTL 描述，在更高的抽象级别上工作。这为解决这些问题提供了一种很有前景的方法。但是，HLS 工具的性能仍然存在局限性。例如，设计人员仍然接触硬件设计的各个方面，开发周期仍然很耗时，而且 HLS 工具的结果质量 (QoR) 远远落后于 RTL 流程。在本文中，我们调查了自 2014 年以来发表的关于 HLS 工具性能优化的文献。与之前的工作相比，我们扩展了 HLS 工具的性能范围，并提出了一套三级评估标准，涵盖从 HLS 工具的易用性到 QoR 特定指标的推广。我们还提出了性能评估方程来描述性能优化和 QoR 之间的关系。我们发现它需要在高效 HLS 工具的易用性上付出更多努力。我们建议最好将HLS开发过程与嵌入式系统设计过程进行类比，并提供集成FPGA虚拟机的更具弹性的HLS方法论。并提出了一套三级评估标准，涵盖从 HLS 工具的易用性到 QoR 特定指标的推广。我们还提出了性能评估方程来描述性能优化和 QoR 之间的关系。我们发现它需要在高效 HLS 工具的易用性上做更多的努力。我们建议最好将HLS开发过程与嵌入式系统设计过程进行类比，并提供集成FPGA虚拟机的更具弹性的HLS方法论。并提出了一套三级评估标准，涵盖从 HLS 工具的易用性到 QoR 特定指标的推广。我们还提出了性能评估方程来描述性能优化和 QoR 之间的关系。我们发现它需要在高效 HLS 工具的易用性上做更多的努力。我们建议最好将HLS开发过程与嵌入式系统设计过程进行类比，并提供集成FPGA虚拟机的更具弹性的HLS方法论。