Abstract Graphene, due to its unique electronic structure favoring high carrier mobility, is considered a promising material for use in high-speed electronic devices in the post-silicon electronic era. For this reason, experimental research on graphene-based field-effect transistors (GFETs) has rapidly increased in the last years. However, despite the continuous progress in the optimization of such devices many critical issues remain to be solved such as their reproducibility and performance uniformity against possible variations originated by the manufacturing processes or the operating conditions. In the present work, changes of the I D - V DS characteristics of a Graphene Field-Effect Transistors, caused by a tolerance of 10% in the active channel (i.e. its length and width) and in the top oxide thickness are numerically investigated in order to assess the reliability of such devices. Design of Experiments (DoE) is adopted with the aim to identify the most influential factors on the electrical performance of the device, so that the fabrication process may be suitably optimized.

中文翻译：

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通过实验设计对石墨烯场效应晶体管进行灵敏度分析

摘要 石墨烯由于其独特的电子结构有利于高载流子迁移率，被认为是后硅电子时代高速电子器件的一种很有前途的材料。因此，基于石墨烯的场效应晶体管 (GFET) 的实验研究在过去几年迅速增加。然而，尽管在优化此类设备方面不断取得进展，但仍有许多关键问题有待解决，例如它们的再现性和性能均匀性，以应对由制造过程或操作条件引起的可能变化。在目前的工作中，石墨烯场效应晶体管的 ID - V DS 特性的变化，由有源通道中 10% 的容差引起（即 其长度和宽度）和顶部氧化层厚度进行了数值研究，以评估此类器件的可靠性。采用实验设计 (DoE) 的目的是确定对器件电气性能影响最大的因素，从而可以适当优化制造工艺。