The Viterbi Algorithm is a recursive optimal solution for estimating the most likely state sequence of discrete-time finite-state Markov process and Hidden Markov Models (HMM) observed in memoryless noise. The Viterbi algorithm is extensively used for decoding convolutional codes, in the constraint length k that encompasses its use in digital communications specifically in satellite and cellular communications. Storage devices to speed up access, speech synthesis and recognition technologies use the Viterbi algorithm or its variants. In this paper low-power, high-speed and reduced transistor count Viterbi decoding circuits with enhanced error detection capabilities are designed and implemented with signature-based error detection schemes in three design logic styles primarily Conventional CMOS, Hybrid logic and GDI. The significance of the work is the upshot of realizing low latency and low power dissipation with high reliability in the iterative process of finding the least path metric by superseding the subtractor in CSA & PCSA circuits with an optimized comparator. When evaluated against the Traditional/Benchmark CSA & PCSA circuits, the Conventional CMOS design approach attains low power consumption and high accuracy with a reduction in average power dissipation by 4.69% and 3.83% and an improvement in delay performance by 7.89% and 3.79% respectively, with a tradeoff for high area utilization. Whereas, the GDI design approach results in an extreme reduction of transistor count by 71.52% and 74.94% with a weaker logic swing for CSA & PCSA units respectively, complimented by an increase in power dissipation (approximately multiplied by a factor of 5) and deterioration in delay performance by one order of magnitude. The Hybrid logic stages CSA & PCSA units that are 32.52% and 9.27% faster and achieve optimization in area utilization by 48.68% and 51.09% respectively, at the expense of elevated power dissipation by one order of magnitude. All the circuits were designed and simulated using GPDK 90 nm technology libraries on Cadence Design Suite 6.1.6 platform at 27 °C temperature on 1.2 V supply-rail and SPICE codes were generated as well.

中文翻译：

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以模块化VLSI设计逻辑风格实现的可靠维特比解码器电路的综合分析和优化

Viterbi 算法是一种递归最优解，用于估计在无记忆噪声中观察到的离散时间有限状态马尔可夫过程和隐马尔可夫模型 (HMM) 的最可能状态序列。Viterbi 算法广泛用于解码卷积码，其约束长度 k 包含其在数字通信中的使用，特别是在卫星和蜂窝通信中。存储设备加速访问、语音合成和识别技术使用维特比算法或其变体。在本文中，具有增强的错误检测能力的低功耗、高速和减少晶体管数量的维特比解码电路设计和实现了基于签名的错误检测方案，主要采用三种设计逻辑风格，主要是传统 CMOS、混合逻辑和 GDI。这项工作的意义在于，通过用优化的比较器取代 CSA 和 PCSA 电路中的减法器，在寻找最小路径度量的迭代过程中，以高可靠性实现低延迟和低功耗。与传统/基准 CSA 和 PCSA 电路相比，传统 CMOS 设计方法实现了低功耗和高精度，平均功耗降低了 4.69% 和 3.83%，延迟性能分别提高了 7.89% 和 3.79% ，以高面积利用率为代价。鉴于 GDI 设计方法导致晶体管数量大幅减少 71.52% 和 74.94%，CSA 和 PCSA 单元的逻辑摆幅分别较弱，功耗增加（大约乘以 5 倍）和延迟性能下降一个数量级。混合逻辑级 CSA 和 PCSA 单元的速度分别提高了 32.52% 和 9.27%，并分别实现了 48.68% 和 51.09% 的面积利用率优化，代价是功耗提高了一个数量级。所有电路均使用 GPDK 90 nm 技术库在 Cadence Design Suite 6.1.6 平台上设计和仿真，温度为 27 °C，供电轨为 1.2 V，并生成 SPICE 代码。以功耗增加一个数量级为代价。所有电路均使用 GPDK 90 nm 技术库在 Cadence Design Suite 6.1.6 平台上设计和仿真，温度为 27 °C，供电轨为 1.2 V，并生成 SPICE 代码。以功耗增加一个数量级为代价。所有电路均使用 GPDK 90 nm 技术库在 Cadence Design Suite 6.1.6 平台上设计和仿真，温度为 27 °C，供电轨为 1.2 V，并生成 SPICE 代码。