Advances in digital communication advocate for the use of hardware LDPC decoders in applications requiring reliable and fast information transfer. Hand-coded RTL architectures provide the highest performances but slower the path to IP design. By the use of HLS-based methodology, a number of approaches exists to facilitate development and to rapidly incorporate hardware accelerators into end-user applications. In this paper we present a generic SystemC behavioral model to generate efficient hardware LDPC decoders using Xilinx Vivado HLS. We evaluate the performance of provided architectures and assess efficiency over competing approaches. Hardware complexity reduction up to 10× are shown whereas the throughput speedups are between 1.5× and 16×. The provided architectures have performance in the same order of magnitude of handcrafted RTL architectures.

数字通信的进步主张在要求可靠和快速的信息传输的应用中使用硬件LDPC解码器。手工编码的RTL体系结构可提供最高的性能，但会降低IP设计的速度。通过使用基于HLS的方法，存在许多促进开发并将硬件加速器快速合并到最终用户应用程序中的方法。在本文中，我们提出了一个通用的SystemC行为模型，以使用Xilinx Vivado HLS生成高效的硬件LDPC解码器。我们评估所提供架构的性能，并评估竞争方法的效率。硬件复杂度降低了10倍，而吞吐速度提高了1.5倍至16倍。