Polar codes are a class of linear block codes that provably achieves channel capacity. They have been selected as a coding scheme for the control channel of enhanced mobile broadband (eMBB) scenario for $5^{\text{th}}$ generation wireless communication networks (5G) and are being considered for additional use scenarios. As a result, fast decoding techniques for polar codes are essential. Previous works targeting improved throughput for successive-cancellation (SC) decoding of polar codes are semi-parallel implementations that exploit special maximum-likelihood (ML) nodes. In this work, we present a new fast simplified SC (Fast-SSC) decoder architecture. Compared to a baseline Fast-SSC decoder, our solution is able to reduce the memory requirements. We achieve this through a more efficient memory utilization, which also enables to execute multiple operations in a single clock cycle. Finally, we propose new special node merging techniques that improve the throughput further, and detail a new Fast-SSC-based decoder architecture to support merged operations. The proposed decoder reduces the operation sequence requirement by up to $39\%$, which enables to reduce the number of time steps to decode a codeword by $35\%$. ASIC implementation results with 65 nm TSMC technology show that the proposed decoder has a throughput improvement of up to $31\%$ compared to previous Fast-SSC decoder architectures.

中文翻译：

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快速极性解码器硬件实现的操作合并

Polar码是一类可证明实现信道容量的线性分组码。它们已被选为 5^{\text{th}}$ 代无线通信网络 (5G) 增强型移动宽带 (eMBB) 场景控制信道的编码方案，并且正在考虑用于其他使用场景。因此，极性码的快速解码技术是必不可少的。以前针对极性码的连续消除 (SC) 解码提高吞吐量的工作是利用特殊最大似然 (ML) 节点的半并行实现。在这项工作中，我们提出了一种新的快速简化 SC（Fast-SSC）解码器架构。与基线 Fast-SSC 解码器相比，我们的解决方案能够减少内存需求。我们通过更有效的内存利用来实现这一目标，它还允许在单个时钟周期内执行多个操作。最后，我们提出了新的特殊节点合并技术，进一步提高了吞吐量，并详细介绍了一种新的基于 Fast-SSC 的解码器架构来支持合并操作。所提出的解码器将操作序列要求降低了 39\%$，这使得解码一个码字的时间步数减少了 35\%$。使用 65 nm TSMC 技术的 ASIC 实现结果表明，与之前的 Fast-SSC 解码器架构相比，所提出的解码器的吞吐量提高了 31% 美元。所提出的解码器将操作序列要求降低了 39\%$，这使得解码一个码字的时间步数减少了 35\%$。使用 65 nm TSMC 技术的 ASIC 实现结果表明，与之前的 Fast-SSC 解码器架构相比，所提出的解码器的吞吐量提高了 31% 美元。所提出的解码器将操作序列要求降低了 39\%$，这使得解码一个码字的时间步数减少了 35\%$。使用 65 nm TSMC 技术的 ASIC 实现结果表明，与之前的 Fast-SSC 解码器架构相比，所提出的解码器的吞吐量提高了 31% 美元。