In this paper, a drain‐engineered double‐gate Tunnel‐FET (DE‐DG‐TFET) to enhance the electrical characteristics and analog parameters of a conventional DG‐TFET is proposed and examined through calibrated TCAD simulations. Unlike DG‐TFET, a constant n‐type doping, N_cd, (5 × 10¹⁷ cm⁻³ − 2 × 10¹⁸ cm⁻³), in the channel/drain regions of DE‐DG‐TFET is used, resulting in a p⁺‐n‐n structure instead of conventional p⁺‐i‐n structure. Further, p⁺‐n‐n is modified to p⁺‐n‐n⁺ using electrostatic doping (ED) method on the drain side with Hafnium (ϕ_m = 3.9 eV) as a lateral (top and bottom) and side metal electrode. A high n⁺‐drain doping ensures the drain contact remains ohmic. Higher electric field at p⁺‐n source‐channel junction enhances the ON‐state BTBT current. While the absence of metallurgical junction provides large tunneling width across the channel/drain junction, resulting in suppression of ambipolar current (I_AMB). At N_cd doping of 1 × 10¹⁸ cm⁻³, DE‐DG‐TFET demonstrates ~7 times increase in I_ON while I_AMB is suppressed by ~5 orders of magnitude. In addition to this, the proposed device improves analog/RF figures of merit, 45% in voltage gain and ~5 times in peak f_T.

中文翻译：

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静电掺杂漏极设计的DG-TFET：建议和分析

本文提出了一种通过漏极设计的双栅极隧道FET（DE-DG-TFET）来增强常规DG-TFET的电气特性和模拟参数，并通过校准的TCAD仿真进行了研究。与DG-TFET不同的是，在DE-DG-TFET的沟道/漏极区中使用恒定的n型掺杂N _cd（5×10 ¹⁷  cm ^-3-2 ×10 ¹⁸  cm ^-3），从而导致ap ⁺ -n -n结构，而不是传统的p ⁺ -i-n结构。此外，P ⁺ -n-n被改性至p ⁺ -n-n的⁺采用静电掺杂（ED）方法与铪漏极侧（ϕ _m = 3.9 eV）作为侧面（顶部和底部）和侧面金属电极。高n ⁺漏极掺杂确保漏极接触保持欧姆性。p ⁺ -n源沟道结处的较高电场会增强BTBT电流的导通状态。尽管没有冶金结，但在沟道/漏极结之间提供了较大的隧穿宽度，从而抑制了双极性电流（I _AMB）。在N _cd掺杂为1×10 ¹⁸  cm ^-3时，DE‐DG‐TFET表现出I _ON增加约7倍，而I _AMB被抑制约5个数量级。除此之外，该器件还改善了模拟/ RF品质因数，电压增益提高了45％，峰值f _T降低了约5倍。