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Hybrid encoding for test data compression
Microprocessors and Microsystems ( IF 2.6 ) Pub Date : 2020-06-04 , DOI: 10.1016/j.micpro.2020.103169
C. Kalamani , M. Mayilsamy , V. Rukkumani , K. Srinivasan , R. Mohan Kumar , K. Paramasivam

Main disputes of digital integrated circuits testing are increasing test data volume and test power. The proposed encoding schemes are a combination of nine coded and selective pattern compression, Alternate Variable Run length code to reduce test data volume. The test cubes are divided into multiples of 8, 16, 32, and 64 blocks to upsurge the relationship among the successive test patterns which offers enriched test data reduction. The test data blocks are encoded with two methods in order to reduce test data volume. In the first method, the test sets are encoded using nine coded with selective pattern coding to expand the test data density. In the second method, the test sets are encoded using nine coded with Alternate variable run length laterally with selective pattern coding to improve the test data compression. Investigational results show that the proposed first and second approaches offer a maximum of 76% and 83% of compression ratio respectively for ISCAS’89 benchmark circuits.



中文翻译:

用于测试数据压缩的混合编码

数字集成电路测试的主要争议是增加测试数据量和测试能力。提出的编码方案是九种编码和选择性模式压缩,交替可变游程长度代码的组合,以减少测试数据量。测试立方体分为8、16、32和64个块的倍数,以增加连续测试模式之间的关系,从而减少了测试数据的数量。为了减少测试数据量,用两种方法对测试数据块进行编码。在第一种方法中,使用具有选择性模式编码的九种编码对测试集进行编码,以扩展测试数据的密度。在第二种方法中,对测试集进行编码,使用九种编码方式,横向编码交替可变游程长度的九种编码方式,并进行选择性模式编码,以改善测试数据压缩率。

更新日期:2020-06-04
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