Information Processing Letters ( IF 0.5 ) Pub Date : 2020-06-04 , DOI: 10.1016/j.ipl.2020.105980 Balagopal Komarath , Nitin Saurabh
Detecting and eliminating logic hazards in Boolean circuits is a fundamental problem in logic circuit design. We show that there is no time algorithm, for any , that detects logic hazards in Boolean circuits of size s on n variables under the assumption that the strong exponential time hypothesis is true. This lower bound holds even when the input circuits are restricted to be formulas of depth four. We also present a polynomial time algorithm for detecting 1-hazards in Dnf (or, 0-hazards in Cnf) formulas. Since 0-hazards in Dnf (or, 1-hazards in Cnf) formulas are easy to eliminate, this algorithm can be used to detect whether a given Dnf or Cnf formula has a hazard in practice.
中文翻译:
关于检测危害的复杂性
检测和消除布尔电路中的逻辑危害是逻辑电路设计中的一个基本问题。我们证明没有 时间算法,适用于任何 ,该函数在强指数时间假设为真的情况下检测n个变量上大小为s的布尔电路中的逻辑危险。即使当输入电路被限制为深度为4的公式时,该下限仍然成立。我们还提出一个多项式时间算法用于检测1-危害DNF(或,O-危害CNF)公式。由于在0灾害DNF(或,1-危害CNF)公式是容易消除,这种算法可用于检测给定是否DNF或CNF式在实践中存在危险。