Abstract In this paper, two digitally-controlled ring oscillators (DROs) with similar structure but different constructive cells have been proposed. These proposed DROs include of 5 stages, and each stage contains 10 parallel delay cells. In addition, each stage has fine and coarse parts for adjusting the output frequency. The proposed designs have a wide frequency range and high frequency. The frequency range of the first DRO changes from 1.566 to 20.25 GHz (92.6%) and for the second DRO, its frequency is from 2.218 to 22.86 GHz (90.31%). By considering all possible digital codes for fine and coarse stages, the power consumption of the first DRO changes from 1.1 to 13.64 mW, while this value for the second DRO varies from 144.1 μW to 1.76 mW. The phase noise of the first DRO at the center frequency of 20.25 GHz and the 1 MHz offset is equal to –76.24 dBc/Hz, and at 10 MHz offset the phase noise is equal to –104 dBc/Hz. The phase noise of the second DRO at the center frequency of 22.86 GHz and the 1 MHz offset is equal to –66.64 dBc/Hz, and at the 10 MHz offset the phase noise is equal to –95.39 dBc/Hz. The proposed DROs have been simulated by using the Cadence software in TSMC 65nm CMOS technology and 1.2 V power supply.

中文翻译：

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用于宽调谐范围应用的数控环形振荡器

摘要 本文提出了两种结构相似但结构单元不同的数控环形振荡器（DRO）。这些提议的 DRO 包括 5 个阶段，每个阶段包含 10 个并行延迟单元。此外，每一级都有用于调整输出频率的细部和粗部。所提出的设计具有宽频率范围和高频。第一个 DRO 的频率范围从 1.566 到 20.25 GHz (92.6%)，第二个 DRO 的频率范围从 2.218 到 22.86 GHz (90.31%)。通过考虑精细和粗略阶段的所有可能数字代码，第一个 DRO 的功耗从 1.1 到 13.64 mW，而第二个 DRO 的这个值从 144.1 μW 到 1.76 mW。中心频率为 20 时第一个 DRO 的相位噪声。25 GHz 和 1 MHz 偏移等于 –76.24 dBc/Hz，10 MHz 偏移时相位噪声等于 –104 dBc/Hz。第二个 DRO 在 22.86 GHz 中心频率和 1 MHz 偏移处的相位噪声等于 –66.64 dBc/Hz，在 10 MHz 偏移处相位噪声等于 –95.39 dBc/Hz。建议的 DRO 已通过使用 Cadence 软件在 TSMC 65nm CMOS 技术和 1.2 V 电源中进行仿真。