Abstract

The results of the TCAD (Technology Computer Aided Design) simulation of 65-nm bulk CMOS combinational logical elements of a triple majority gate (TMG) for a reliable microprocessor redundant system are presented. The AND and the OR logic elements, each of which consists of NAND and NOR elements and pairs of inverters, topologically located before and after the line of transistors of each of NAND and of NOR elements, are more noise-immune to single transient processes under the impact of single ionizing particles due to the minimization of the duration of the noise pulse by partially compensating them during the simultaneous charge collection from the track of a single nuclear particle. In simulation with TCAD tools, the tracks of the particles along the normal to the chip surface are used. The charge collection by logical elements with compensation when a linear transfer of particle energy to the track of up to 60 MeV cm²/mg leads to a reduction of the duration of the pulse noise at the output of CMOS AND (and OR) elements by factors of 2 to 5.

中文翻译：

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单电离粒子对CMOS三多数栅极逻辑元件的影响建模

摘要

给出了针对可靠的微处理器冗余系统的三重多数门（TMG）的65 nm批量CMOS组合逻辑元件的TCAD（技术计算机辅助设计）仿真结果。“与”和“或”逻辑元件分别由“与非”和“或非”元件以及成对的反相器组成，拓扑结构分别位于“与非”和“或非”元件的晶体管行的前后。单个电离粒子的影响是由于在从单个核粒子的轨迹同时收集电荷的过程中通过部分补偿它们而使噪声脉冲的持续时间最小化所致。在使用TCAD工具进行仿真时，将使用沿芯片表面法线的粒子轨迹。² / mg导致CMOS AND（或OR）元件输出的脉冲噪声持续时间减少2到5倍。