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SALE: Smartly Allocating Low-Cost Many-Bit ECC for Mitigating Read and Write Errors in STT-RAM Caches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems ( IF 2.8 ) Pub Date : 2020-06-01 , DOI: 10.1109/tvlsi.2020.2977131
Muhammad Avais Qureshi , Jungwoo Park , Soontae Kim

Spin-transfer torque RAM (STT-RAM) is a future technology for ON-chip caches. However, it suffers from high read and write error rates. Concurrently dealing with these errors is quite challenging and incurs large performance overhead. This article proposes a smartly allocating low-cost many-bit ECC (SALE) scheme, which makes use of the low-cost many-bit error correction coding (ECC) to overcome this performance overhead. The low-cost many-bit ECC can fix many errors with low logic complexity and latency overheads. However, it requires a large number of parity bits. Therefore, SALE smartly uses low-cost many-bit ECC for only a certain type of cache lines and manages the corresponding large number of parity bits in the data array. SALE also introduces an ECC-free partition to reduce the ECC storage requirement for the STT-RAM caches. The cache lines belonging to an ECC-free partition do not have dedicated storage space for the ECC parity bits, thereby reducing the ECC storage requirement for the STT-RAM caches. Our experimental results demonstrate that SALE achieves performance close to that of an error-free cache by improving performance by 13% (16%) over the baseline scheme in single-core (quad-core) systems while requiring 50% less storage space for the ECC parity bits.

中文翻译:

销售:智能分配低成本多位 ECC 以减少 STT-RAM 缓存中的读取和写入错误

自旋转移矩 RAM (STT-RAM) 是片上缓存的未来技术。但是,它的读写错误率很高。同时处理这些错误非常具有挑战性,并且会产生大量的性能开销。本文提出了一种智能分配低成本多位 ECC (SALE) 方案,该方案利用低成本多位纠错编码 (ECC) 来克服这种性能开销。低成本的多位 ECC 可以以低逻辑复杂度和延迟开销修复许多错误。然而,它需要大量的奇偶校验位。因此,SALE 巧妙地将低成本的多位 ECC 仅用于某种​​类型的缓存行,并管理数据阵列中相应的大量奇偶校验位。SALE 还引入了一个无 ECC 分区,以减少 STT-RAM 缓存的 ECC 存储要求。属于无 ECC 分区的缓存行没有用于 ECC 奇偶校验位的专用存储空间,从而减少了 STT-RAM 缓存的 ECC 存储需求。我们的实验结果表明,在单核(四核)系统中,SALE 通过将性能提高 13% (16%) 比基准方案提高了 13% (16%) 的性能,同时减少了 50% 的存储空间用于ECC 奇偶校验位。
更新日期:2020-06-01
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