Digital signal processing (DSP) on field-programmable gate arrays (FPGAs) has long been appealing because of the inherent parallelism in these computations that can be easily exploited to accelerate such algorithms. FPGAs have evolved significantly to further enhance the mapping of these algorithms, included additional hard blocks, such as the DSP blocks found in modern FPGAs. Although these DSP blocks can offer more efficient mapping of DSP computations, they are primarily designed for 1-D filter structures. We present a study on spatial convolutional filter implementations on FPGAs, optimizing around the structure of the DSP blocks to offer high throughput while maintaining the coefficient flexibility that other published architectures usually sacrifice. We show that it is possible to implement large filters for large 4K resolution image frames at frame rates of 30–60 FPS, while maintaining functional flexibility.

中文翻译：

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FPGA 上的高吞吐量空间卷积滤波器

长期以来，现场可编程门阵列 (FPGA) 上的数字信号处理 (DSP) 一直很有吸引力，因为这些计算中固有的并行性很容易被利用来加速此类算法。FPGA 已经显着发展，以进一步增强这些算法的映射，包括额外的硬块，例如现代 FPGA 中的 DSP 块。尽管这些 DSP 模块可以提供更有效的 DSP 计算映射，但它们主要是为一维滤波器结构设计的。我们对 FPGA 上的空间卷积滤波器实现进行了研究，围绕 DSP 块的结构进行优化以提供高吞吐量，同时保持其他已发布架构通常会牺牲的系数灵活性。