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Thermal-aware detour routing in 3D NoCs
Journal of Parallel and Distributed Computing ( IF 3.8 ) Pub Date : 2020-05-30 , DOI: 10.1016/j.jpdc.2020.04.010
Priyajit Mukherjee , Navonil Chatterjee , Santanu Chattopadhyay

Three-dimensional Network-on-Chips (3D NoCs) is a popular design choice due to its low packet latency, low network power consumption and high packing density. However, 3D NoCs suffer from high temperature issues. The 3D stacking of Si-layers elongates heat transfer path from different Si-layers to the heat sink resulting in increase in peak temperature of the chip. Since routers of NoCs have high power densities, a higher router activity may result in signification increase in temperature of the chip. Therefore, a judicious selection of the routing path is necessary to reduce the chip temperature. As the routers placed at the lower Si-layers have higher thermal conductance to the heat sink, a routing path consisting of more number of routers in the lower Si-layers may improve the temperature profile of the chip. In this paper, we have proposed two different thermal-aware routing approaches, which use downward detoured routing for some optimally selected communication paths to reduce the chip temperature. The first technique is a thermal-aware application-specific Mixed Integer Linear Programming based method (named TMD), while the second one is an application-agnostic heuristic approach (named TSD). To predict the effect of detour decisions on the temperature profile of the chip, TMD technique has applied two different thermal models with a constraint on the average packet delay (APD) of the network. Experimental results show that a significant temperature reduction (up to 22) can be achieved within minimal performance loss (10% increase in APD) using either of the proposed techniques, compared to the minimal path routing algorithms – XYZ, ZXY and EDGE and the greedy detour approaches – All Detour and Random Detour.



中文翻译:

3D NoC中的热感知绕行路由

三维片上网络(3D NoC)由于其低数据包延迟,低网络功耗和高封装密度而成为一种流行的设计选择。但是,3D NoC遭受高温问题。Si层的3D堆叠延长了从不同的Si层到散热器的传热路径,从而导致芯片的峰值温度升高。由于NoC路由器具有较高的功率密度,因此较高的路由器活动可能会导致芯片温度明显升高。因此,必须明智地选择布线路径以降低芯片温度。由于放置在较低Si层上的路由器对散热器的导热性更高,因此在较低Si层中由更多数量的路由器组成的路由路径可以改善芯片的温度曲线。在本文中,我们提出了两种不同的热感知路由方法,它们对某些最佳选择的通信路径使用向下绕行的路由,以降低芯片温度。第一种技术是基于热感知的特定于应用的混合整数线性规划方法(称为TMD),而第二种技术是与应用无关的启发式方法(称为TSD)。为了预测绕行决策对芯片温度曲线的影响,TMD技术已应用了两个不同的热模型,这些模型对网络的平均数据包延迟(APD)有所限制。实验结果表明,温度明显降低(最高可达22 第一种技术是基于热感知的特定于应用的混合整数线性规划方法(称为TMD),而第二种技术是与应用无关的启发式方法(称为TSD)。为了预测绕行决策对芯片温度曲线的影响,TMD技术已应用了两个不同的热模型,这些模型对网络的平均数据包延迟(APD)有所限制。实验结果表明,温度明显降低(最高可达22 第一种技术是基于热感知的特定于应用的混合整数线性规划方法(称为TMD),而第二种技术是与应用无关的启发式方法(称为TSD)。为了预测绕行决策对芯片温度曲线的影响,TMD技术已应用了两个不同的热模型,这些模型对网络的平均数据包延迟(APD)有所限制。实验结果表明,温度明显降低(最高可达22与最小路径路由算法XYZ,ZXY和EDGE以及贪婪绕行方法(全部绕行和随机绕行)相比,使用两种建议的技术都可以在最小的性能损失(APD增加10%)的情况下实现)。

更新日期:2020-05-30
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