当前位置: X-MOL 学术IEEE Embed. Syst. Lett. › 论文详情
Our official English website, www.x-mol.net, welcomes your feedback! (Note: you will need to create a separate account there.)
An Accurate and Quick ANN based System-Level Dynamic Power Estimation Model using LLVM IR Profiling for FPGA Designs
IEEE Embedded Systems Letters ( IF 1.6 ) Pub Date : 2020-06-01 , DOI: 10.1109/les.2019.2935052
Abhishek N. Tripathi , Arvind Rajawat

The demand of early estimation of the power of semiconductor devices has risen due to technology scaling, growing complexity, and faster time to market. In this letter, we present the early power estimation model for field programmable gate array-based designs. We perform the profiling at C-level using low-level virtual machine intermediate representation and then training of the neural network from the profiling information to create the estimation model. The model accuracy is validated from the CHStone, MachSuite, and Rosetta-master benchmark applications. An insignificant relative error of 0.21% to 5.12% is observed for the analyzed benchmark designs with the exceptional increase in estimation speed by 87 times of magnitude as compared to the Xilinx Vivado Design Suite.

中文翻译:

使用 LLVM IR 分析的基于 ANN 的准确快速的系统级动态功耗估计模型用于 FPGA 设计

由于技术规模化、复杂性增加和上市时间加快,对半导体器件功率的早期估计的需求已经上升。在这封信中,我们介绍了基于现场可编程门阵列的设计的早期功率估计模型。我们使用低级虚拟机中间表示在 C 级执行分析,然后根据分析信息训练神经网络以创建估计模型。模型准确性已通过 CHStone、MachSuite 和 Rosetta-master 基准测试应用程序验证。与赛灵思 Vivado 设计套件相比,所分析的基准设计具有 87 倍的显着提高估计速度,观察到 0.21% 至 5.12% 的微不足道的相对误差。
更新日期:2020-06-01
down
wechat
bug