Gate-all-around Vertical Nanowire Field Effect Transistors (VNWFET) are emerging devices, which are well suited to pursue scaling beyond lateral scaling limitations around 7nm. This work explores the relative merits and drawbacks of the technology in the context of logic cell design. We describe a junctionless nanowire technology and associated compact model, which accurately describes fabricated device behavior in all regions of operations for transistors based on between 16 and 625 parallel nanowires of diameters between 22 and 50nm. We used this model to simulate the projected performance of inverter logic gates based on passive load, active load and complementary topologies and carry out an performance exploration for the number of nanowires in transistors. In terms of compactness, through a dedicated full 3D layout design, we also demonstrate a 1.4x reduction in lateral dimensions for the complementary structure with respect to 7nm FinFET-based inverters.

中文翻译：

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基于垂直 NWFET 技术的 3D 逻辑单元设计和结果，包括绑定紧凑模型

全栅极垂直纳米线场效应晶体管 (VNWFET) 是新兴器件，非常适合追求超越 7nm 左右横向缩放限制的缩放。这项工作在逻辑单元设计的背景下探索了该技术的相对优点和缺点。我们描述了一种无结纳米线技术和相关的紧凑模型，它准确地描述了基于 16 到 625 条直径在 22 到 50 纳米之间的平行纳米线的晶体管在所有操作区域中制造的器件行为。我们使用该模型来模拟基于无源负载、有源负载和互补拓扑的逆变器逻辑门的预计性能，并对晶体管中的纳米线数量进行性能探索。在紧凑性方面，通过专用的全3D布局设计，