Abstract In this paper, we investigate the single and repetitive avalanche performance and characteristics of different SiC device technologies including SiC cascode JFETs and SiC Trench MOSFETs. SiC Cascode JFETs exhibit a different failure mode from SiC MOSFETs due to the interaction between the low-voltage (LV) silicon MOSFET and the high-voltage (HV) SiC JFET through the resistance connecting the MOSFET source to the JFET gate. MOSFETs fail in avalanche typically due to parasitic BJT latch-up and/or thermal hot-spotting leading to a source-to-drain short. However, cascode JFETs can fail with the low voltage MOSFET still functional and a low resistance measured between the cascode terminals. The failure point of SiC Cascode JFETs in avalanche is therefore not clearly identifiable and the failure criteria will have to be reassessed. Measurements and simulations show that the connection between the JFET gate and the MOSFET source influences the avalanche duration and avalanche power. Finite element simulations show that increased leakage through the gate resistance of the SiC JFET at higher temperatures causes delayed transients in the VDS turn-OFF. Hence, the result is low-voltage avalanche turn-OFF where only the LV silicon MOSFET goes into avalanche and the JFET goes into linear mode. SiC Cascode JFETs show reduced performance under repetitive avalanche due to degradation of the JFET gate resistance and increased linear mode conduction of the SiC JFET. Failure analysis proves that the low voltage silicon MOSFET is unaffected while the avalanche current flows through the SiC JFET gate which appears to be shorted.

中文翻译：

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单次和重复雪崩脉冲下 SiC 共源共栅 JFET 的性能

摘要 在本文中，我们研究了包括 SiC 共源共栅 JFET 和 SiC 沟槽 MOSFET 在内的不同 SiC 器件技术的单次和重复雪崩性能和特性。由于低压 (LV) 硅 MOSFET 和高压 (HV) SiC JFET 通过将 MOSFET 源极连接到 JFET 栅极的电阻之间的相互作用，SiC 级联 JFET 表现出与 SiC MOSFET 不同的故障模式。MOSFET 在雪崩中失效通常是由于寄生 BJT 闩锁和/或热热点导致源漏短路。然而，共源共栅 JFET 可能会因低压 MOSFET 仍然起作用并且在共源共栅端子之间测量到低电阻而发生故障。因此，无法明确识别雪崩中 SiC 级联 JFET 的故障点，必须重新评估故障标准。测量和仿真表明，JFET 栅极和 MOSFET 源极之间的连接会影响雪崩持续时间和雪崩功率。有限元仿真表明，在较高温度下通过 SiC JFET 栅极电阻增加的泄漏会导致 VDS 关断中的延迟瞬变。因此，结果是低压雪崩关断，其中只有 LV 硅 MOSFET 进入雪崩，而 JFET 进入线性模式。由于 JFET 栅极电阻的退化和 SiC JFET 的线性模式传导增加，SiC 级联 JFET 在重复雪崩下表现出降低的性能。故障分析证明，当雪崩电流流过似乎短路的 SiC JFET 栅极时，低压硅 MOSFET 不受影响。