In this work, for the first time, the DC characteristics and Analog/RF performance of negative capacitance (NC) Silicon-on-insulator (SOI) junctionless transistor (JLT) have been investigated including quantum confinement effects. In NC transistors, ferroelectric materials are used in the gate-stack to improve the switching characteristics. The Metal-Ferroelectric-Metal-Insulator-semiconductor (MFMIS) gate-stack structure has been simulated with the help of 1D Landau Khalatnikov (LK) equation to incorporate the effect of negative capacitance with SOI JLT. The impact of varying the temperatures in the range 300–380 K and ferroelectric layer thickness ($t_f$) of 0 to 4.5 nm on the device characteristics are studied. The analog and RF characteristics such as transconductance ($g_m$) and cut-off frequency ($f_t$) of NC SOI JLT show better performance over SOI JLT. A minimum subthreshold swing (SS) of 12.77 mV/decade and $f_t$ of 590 GHz has been observed at 300 K for a channel length (L) of 14 nm with $t_f$of 4.5 nm. The characteristics of NC SOI JLT are evaluated by coupling the 1D LK equation with the simulated results of SOI JLT which are obtained using 2D device simulator Atlas^TM from Silvaco.

在这项工作中，首次研究了负电容（NC）绝缘体上硅（SOI）无结晶体管（JLT）的直流特性和模拟/ RF性能，其中包括量子限制效应。在NC晶体管中，铁电材料用于栅堆叠中以改善开关特性。利用一维Landau Khalatnikov（LK）方程对金属-铁电金属-绝缘体-半导体（MFMIS）栅堆叠结构进行了模拟，以将负电容效应与SOI JLT结合在一起。温度在300–380 K和铁电层厚度范围内变化的影响（${Ť}_F$研究了0至4.5nm的器件特性。模拟和RF特性，例如跨导（$G_{米}$）和截止频率（$F_{Ť}$）的NC SOI JLT显示出比SOI JLT更好的性能。最小亚阈值摆幅（SS）为12.77 mV /十倍频程$F_{Ť}$在300 K的情况下，对于14 nm的通道长度（L）观察到了590 GHz的频率。${Ť}_F$4.5纳米。通过将一维LK方程与SOI JLT的仿真结果耦合起来，可以评估NC SOI JLT的特性，该仿真结果是使用Silvaco的2D设备模拟器Atlas ^TM获得的。