This paper presents an energy-efficient low power 10-b 8-MS/s asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter. An inverted common-mode charge recovery technique is proposed to reduce the switching energy and to improve the linearity of the digital-to-analog converter (DAC). The proposed switching technique consumes only 149 CV_REF² switching energy for the 10-bit case. A rail-to-rail dynamic latch comparator is implemented with adaptive power control for better power efficiency. Additionally, to optimize the power consumption and performance of the logic part, a modified asynchronous type SAR control logic with digitally controllable delay cells is adopted. An on-chip reference voltage generator is also designed with an ADC core for practical use. The structure is realized using 55-nm complementary metal–oxide–semiconductor (CMOS) process technology. The proposed architecture achieves an effective number of bits (ENOB) of 9.56 bits and a signal-to-noise and distortion ratio (SNDR) level of 59.3 dB with a sampling rate of 8 MS/s at measurement level. The whole architecture consumes only 572 µW power when a power supply of 1 V is applied.

中文翻译：

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具有片内基准电压发生器的低功耗10-b 8-MS / s异步SAR ADC的设计

本文提出了一种高能效的低功耗10-b 8-MS / s异步逐次逼近寄存器（SAR）模数（ADC）转换器。提出了一种反向共模电荷恢复技术，以降低开关能量并改善数模转换器（DAC）的线性度。拟议的开关技术仅消耗149 CV _REF ²10位情况下的开关能量。轨到轨动态锁存比较器通过自适应功率控制实现，以提高功率效率。另外，为了优化逻辑部分的功耗和性能，采用了具有数字可控延迟单元的改进的异步型SAR控制逻辑。片上参考电压发生器还设计有ADC内核，供实际使用。该结构使用55 nm互补金属氧化物半导体（CMOS）工艺技术实现。所提出的架构实现了9.56位的有效位数（ENOB）和59.3 dB的信噪比和失真比（SNDR）级别，并且在测量级别上的采样率为8 MS / s。施加1 V电源时，整个架构仅消耗572 µW功率。