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Effects of traps in the gate stack on the small-signal RF response of III-V nanowire MOSFETs
Solid-State Electronics ( IF 1.7 ) Pub Date : 2020-05-23 , DOI: 10.1016/j.sse.2020.107840
Markus Hellenbrand , Erik Lind , Olli-Pekka Kilpi , Lars-Erik Wernersson

We present a detailed study of the effect of gate-oxide-related defects (traps) on the small-signal radio frequency (RF) response of III-V nanowire MOSFETs and find that the effects are clearly identifiable in the measured admittance parameters and in important design parameters such as h21 (forward current gain) and MSG (maximum stable gain). We include the identified effects in a small-signal model alongside results from previous investigations of III-V RF MOSFETs and thus provide a comprehensive physical small-signal RF model for this type of transistor, which accurately describes the measured admittance parameters and gains. We verify the physical basis of the model assumptions by calculating the oxide defect density from the measured admittances.



中文翻译:

栅堆叠中的陷阱对III-V纳米线MOSFET小信号RF响应的影响

我们对栅极氧化物相关的缺陷(陷阱)对III-V纳米线MOSFET的小信号射频(RF)响应的影响进行了详细研究,发现在所测得的导纳参数和导纳中可以清楚地识别出这种影响。重要的设计参数,例如 H21(正向电流增益)和MSG(最大稳定增益)。我们将识别出的效应与先前对III-V RF MOSFET的研究结果一起纳入小信号模型中,从而为此类晶体管提供了全面的物理小信号RF模型,该模型准确地描述了测得的导纳参数和增益。我们通过从测得的导纳计算氧化物缺陷密度,验证了模型假设的物理基础。

更新日期:2020-05-23
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