Various self-powered devices employ energy-harvesting technology to capture and store an ambient energy. The photovoltaic (PV) cell is one of the most preferred approaches due to its potential for on-chip integration. Although serial connection of multiple PV cells is commonly required to obtain a sufficiently high voltage for circuit operation, a voltage boosting with serially stacked PV cells is limited in a standard bulk CMOS process because all the PV cells are intrinsically connected to the common substrate. It is possible to increase the output voltage by stacking multiple PV cells with a large area ratio between stages. However, nonoptimal design results in a poor conversion efficiency or a limited open-circuit voltage, making it unsuitable for practical applications. This article proposes a stacking structure and its optimal design method for PV cell stacking in a triple-well CMOS process. The proposed approach utilizes an additional current-sourcing photodiode and an optical filter, which allow high voltage generation without a significant efficiency degradation. The test chip with four-stage stacked PV cells was fabricated using a 0.25- $\mu \text{m}$ standard triple-well CMOS process. The experimental results demonstrate an output voltage of 1.6 V and an electrical power of 263 nW/mm² under an incident illumination with an intensity of $96~\mu \text{W}$ /mm², achieving a responsivity of 1.91 mA/W and a conversion efficiency of 0.27%.

中文翻译：

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三阱CMOS工艺中光伏电池堆叠的设计优化

各种自供电设备采用能量收集技术来捕获和存储环境能量。光伏 (PV) 电池是最优选的方法之一，因为它具有片上集成的潜力。虽然通常需要串联多个 PV 电池以获得足够高的电压以用于电路操作，但是在标准体 CMOS 工艺中，串联堆叠的 PV 电池的电压提升受到限制，因为所有 PV 电池本质上都连接到公共衬底。通过堆叠多个级间面积比较大的光伏电池，可以提高输出电压。然而，非优化设计会导致转换效率差或开路电压有限，使其不适用于实际应用。本文针对三阱CMOS工艺中的光伏电池堆叠提出了一种堆叠结构及其优化设计方法。所提出的方法利用了一个额外的电流源光电二极管和一个光学滤波器，它们允许产生高电压而不会显着降低效率。具有四级堆叠 PV 电池的测试芯片是使用 0.25- $\mu \text{m}$ 标准三阱 CMOS 工艺。实验结果表明，在强度为1.6 V的入射光照下，输出电压为 1.6 V，电功率为 263 nW/mm ² $96~\mu \text{W}$ /mm ²，实现了1.91 mA/W的响应度和0.27%的转换效率。